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    Method of fabricating a semiconductor device
    11.
    发明授权
    Method of fabricating a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06569743B2

    公开(公告)日：2003-05-27

    申请号：US09892996

    申请日：2001-06-28

    申请人： Yong Park ,  Han-Soo Kim

    发明人： Yong Park ,  Han-Soo Kim

    IPC分类号： H01L21336

    CPC分类号： H01L21/28518 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/66659

    摘要： A method of fabricating a semiconductor device is provided. In this method, a gate insulating layer and a gate are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is formed by ion-implanting a first impurity of the second conductivity type at a first dose, using the gate as a mask. Sidewall spacers are formed of an insulating material on the sidewalls of the gate. A second active region of the second conductivity type is formed by masking a narrow region between gates and ion-implanting a second impurity of the second conductivity type at a second dose higher than the first dose. Finally, a silicide layer is formed on the exposed first and second active regions and gate. There exist no impurities in excess of their solid solubility limit, which could block the diffusion of silicon in the narrow region. As a result, a reliable silicidation is ensured.

    摘要翻译： 提供一种制造半导体器件的方法。 在这种方法中，栅极绝缘层和栅极依次形成在第一导电类型的半导体衬底上。 通过使用栅极作为掩模，以第一剂量离子注入第二导电类型的第一杂质形成第二导电类型的第一有源区。 侧壁间隔物由栅极的侧壁上的绝缘材料形成。 通过掩蔽栅极之间的窄区域并以高于第一剂量的第二剂量离子注入第二导电类型的第二杂质来形成第二导电类型的第二有源区。 最后，在暴露的第一和第二有源区域和栅极上形成硅化物层。 不存在超过其固溶度极限的杂质，这可能阻止硅在狭窄区域的扩散。 结果，确保了可靠的硅化。

    Vertical type semiconductor devices
    12.
    发明授权
    Vertical type semiconductor devices 有权
    垂直型半导体器件

    公开(公告)号：US09306041B2

    公开(公告)日：2016-04-05

    申请号：US14156607

    申请日：2014-01-16

    申请人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    发明人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    IPC分类号： H01L29/66 ,  H01L29/792 ,  H01L27/115

    CPC分类号： H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

    摘要： A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

    摘要翻译： 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

    Methods of manufacturing a semiconductor device
    13.
    发明授权
    Methods of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09087861B2

    公开(公告)日：2015-07-21

    申请号：US14156781

    申请日：2014-01-16

    申请人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    发明人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

    摘要翻译： 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步的阶梯状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。

    INKJET COMPOSITION FOR FORMING A TRANSPARENT FILM, AND TRANSPARENT FILM FORMED FROM SAME
    15.
    发明申请
    INKJET COMPOSITION FOR FORMING A TRANSPARENT FILM, AND TRANSPARENT FILM FORMED FROM SAME 审中-公开
    用于形成透明膜的喷墨组合物和从其形成的透明膜

    公开(公告)号：US20120178863A1

    公开(公告)日：2012-07-12

    申请号：US13395844

    申请日：2010-09-10

    申请人： Mun-Ho Kim ,  Seung-Hee Lee ,  Han-Soo Kim ,  Min-A Yu ,  Dae-Hyun Kim

    发明人： Mun-Ho Kim ,  Seung-Hee Lee ,  Han-Soo Kim ,  Min-A Yu ,  Dae-Hyun Kim

    IPC分类号： C08K5/103 ,  C08K5/101 ,  C09D133/08

    CPC分类号： G02B5/3033 ,  C08F4/06 ,  C09D11/101 ,  C09D133/10 ,  G02B1/04 ,  C08L33/10 ,  C08L33/08

    摘要： An inkjet composition for a transparent film includes a) a binder polymer, b) a polymerizable monomer, c) a polymerization initiator, and d) a solvent having a boiling point of 150° C. or more. Using the inkjet composition according to the embodiments of the present invention, the transparent film may be directly manufactured at a desired position by using the inkjet process, while using a small amount of ink, thereby increasing the efficiency of the manufacturing process. Also, due to the excellent jetting properties thereof, it is advantageous to forming the transparent film. Furthermore, the excellent transmittance and heat resistance may be obtained.

    摘要翻译： 用于透明膜的喷墨组合物包括a）粘合剂聚合物，b）可聚合单体，c）聚合引发剂，和d）沸点为150℃或更高的溶剂。 使用根据本发明的实施方案的喷墨组合物，可以通过使用喷墨工艺在所需位置直接制造透明膜，同时使用少量的油墨，从而提高制造工艺的效率。 此外，由于其优异的喷射性能，有利的是形成透明膜。 此外，可以获得优异的透射率和耐热性。

    Tooth Whitener
    16.
    发明申请
    Tooth Whitener 审中-公开
    牙齿美白

    公开(公告)号：US20120134936A1

    公开(公告)日：2012-05-31

    申请号：US13345092

    申请日：2012-01-06

    申请人： Sang-Hoon Kwak ,  Sei-Young Yun ,  Kyo-Tae Moon ,  Sang-Nyun Kim ,  Han-Soo Kim ,  Sug-Youn Chang

    发明人： Sang-Hoon Kwak ,  Sei-Young Yun ,  Kyo-Tae Moon ,  Sang-Nyun Kim ,  Han-Soo Kim ,  Sug-Youn Chang

    IPC分类号： A61K8/90 ,  A61K8/73 ,  A61Q11/00 ,  A61K8/86

    CPC分类号： A61K8/064 ,  A61K8/22 ,  A61K8/375 ,  A61K8/8176 ,  A61K8/86 ,  A61Q11/00

    摘要： A tooth whitener is provided, including a water-in-oil (W/O) emulsion phase including: a discontinuous phase comprising a peroxide, a hydrophilic solvent, and a polyol, and a continuous phase comprising a glycerol monooleate, a polymer and a polyol, wherein the tooth whitener is flowable upon being applied to teeth and is solidified by the action of moisture after being applied to teeth, and then is adhered and fixed to teeth, and wherein the glycerol monooleate is in an amount of 15% to 95% by weight, based on total weight of the tooth whitener composition.

    摘要翻译： 提供了一种牙齿增白剂，其包括油包水（W / O）乳液相，其包括：包含过氧化物，亲水性溶剂和多元醇的不连续相，以及包含甘油单油酸酯，聚合物和 多元醇，其中所述牙齿增白剂在施用于牙齿时可流动，并且在施用于牙齿之后通过湿气的作用而固化，然后粘附并固定到牙齿上，并且其中甘油单油酸酯的量为15％至95 重量％，基于牙齿增白剂组合物的总重量。

    Semiconductor device
    18.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20090315187A1

    公开(公告)日：2009-12-24

    申请号：US12457290

    申请日：2009-06-05

    申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

    发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

    IPC分类号： H01L23/522

    CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

    摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

    Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof
    19.
    发明申请
    Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof 有权
    多层非易失性存储器件，采用这种器件的存储器系统及其制造方法

    公开(公告)号：US20090315095A1

    公开(公告)日：2009-12-24

    申请号：US12456391

    申请日：2009-06-16

    申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

    摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

    摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。