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    METHOD FOR MANUFACTURING COLOR FILTER AND COLOR FILTER MANUFACTURED BY USING THE SAME
    3.
    发明申请
    METHOD FOR MANUFACTURING COLOR FILTER AND COLOR FILTER MANUFACTURED BY USING THE SAME 有权
    制造彩色滤光片的方法及使用其制造的彩色滤光片

    公开(公告)号：US20100062377A1

    公开(公告)日：2010-03-11

    申请号：US12450549

    申请日：2008-03-06

    申请人： Dae-Hyun Kim ,  Dong-Chang Choi ,  Kyung-Soo Choi ,  Ho-Chan Ji ,  Hyun-Sik Kim ,  Geun-Young Cha ,  Sung-Hyun Kim ,  Jae-Joon Kim ,  Min-A Yu ,  Mi-Ae Kim ,  Mi-Kyoung Kim

    发明人： Dae-Hyun Kim ,  Dong-Chang Choi ,  Kyung-Soo Choi ,  Ho-Chan Ji ,  Hyun-Sik Kim ,  Geun-Young Cha ,  Sung-Hyun Kim ,  Jae-Joon Kim ,  Min-A Yu ,  Mi-Ae Kim ,  Mi-Kyoung Kim

    IPC分类号： G03F7/00 ,  G02B5/20

    CPC分类号： G02B5/201

    摘要： The present invention relates to a method for manufacturing a color filter and a color filter manufactured by using the same. More particularly, the present invention pertains to a method for manufacturing a color filter, which includes performing plasma treatment of a black matrix (BM) pattern formed on a substrate to increase a difference in ink repellency of the black matrix pattern and a pixel unit, and a color filter manufactured by using the same. When the production method of the present invention is used, it is possible to provide the color filter in which color mixing does not occur in a pixel unit or between pixel units during discharging of ink by using an inkjet printing process, discoloration due to unfilling does not occur, a surface is uniform, and there is an insignificant step in the pixel unit or between the pixel units.

    摘要翻译： 本发明涉及一种制造滤色器的方法和使用该滤色器制造的滤色器。 更具体地说，本发明涉及一种彩色滤光片的制造方法，其特征在于，对形成在基板上的黑矩阵（BM）图案进行等离子体处理，以增加黑矩阵图案和像素单元的斥墨性差异， 以及使用该滤色器制造的滤色片。 当使用本发明的制造方法时，可以提供一种滤色器，其中通过使用喷墨印刷方法在墨水排出期间在像素单元中或在墨水排出期间不在像素单元之间进行混色，其中由于不充分而变色 不发生，表面是均匀的，并且在像素单元中或像素单元之间存在微不足道的步骤。

    Method for manufacturing color filter and color filter manufactured by using the same
    4.
    发明授权
    Method for manufacturing color filter and color filter manufactured by using the same 有权
    制造使用该滤色器的滤色器和滤色器的方法

    公开(公告)号：US08597861B2

    公开(公告)日：2013-12-03

    申请号：US12450549

    申请日：2008-03-06

    申请人： Dae-Hyun Kim ,  Dong-Chang Choi ,  Kyung-Soo Choi ,  Ho-Chan Ji ,  Hyun-Sik Kim ,  Geun-Young Cha ,  Sung-Hyun Kim ,  Jae-Joon Kim ,  Min-A Yu ,  Mi-Ae Kim ,  Mi-Kyoung Kim

    发明人： Dae-Hyun Kim ,  Dong-Chang Choi ,  Kyung-Soo Choi ,  Ho-Chan Ji ,  Hyun-Sik Kim ,  Geun-Young Cha ,  Sung-Hyun Kim ,  Jae-Joon Kim ,  Min-A Yu ,  Mi-Ae Kim ,  Mi-Kyoung Kim

    IPC分类号： G02B5/20

    CPC分类号： G02B5/201

    摘要： The present invention relates to a method for manufacturing a color filter and a color filter manufactured by using the same. More particularly, the present invention pertains to a method for manufacturing a color filter, which includes performing plasma treatment of a black matrix (BM) pattern formed on a substrate to increase a difference in ink repellency of the black matrix pattern and a pixel unit, and a color filter manufactured by using the same. When the production method of the present invention is used, it is possible to provide the color filter in which color mixing does not occur in a pixel unit or between pixel units during discharging of ink by using an inkjet printing process, discoloration due to unfilling does not occur, a surface is uniform, and there is an insignificant step in the pixel unit or between the pixel units.

    摘要翻译： 本发明涉及一种制造滤色器的方法和使用该滤色器制造的滤色器。 更具体地说，本发明涉及一种彩色滤光片的制造方法，其特征在于，对形成在基板上的黑矩阵（BM）图案进行等离子体处理，以增加黑矩阵图案和像素单元的斥墨性差异， 以及使用该滤色器制造的滤色片。 当使用本发明的制造方法时，可以提供一种滤色器，其中通过使用喷墨印刷方法在墨水排出期间在像素单元中或在墨水排出期间不在像素单元之间进行混色，其中由于不充分而变色 不发生，表面是均匀的，并且在像素单元中或像素单元之间存在微不足道的步骤。

    MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI)
    6.
    发明申请
    MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI) 失效
    监测负偏差温度不稳定性（NBTI）和/或正偏差温度不稳定性（PBTI）

    公开(公告)号：US20120182079A1

    公开(公告)日：2012-07-19

    申请号：US13009649

    申请日：2011-01-19

    申请人： Jae-Joon Kim ,  Rahul M. Rao

    发明人： Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： H03K3/03 ,  G06F17/50

    CPC分类号： H03K3/0315 ,  G06F2217/80

    摘要： A ring oscillator circuit for measurement of negative bias temperature instability effect and/or positive bias temperature instability effect includes a ring oscillator having first and second rails, and an odd number (at least 3) of repeating circuit structures. Each of the repeating circuit structures in turn includes an input terminal and an output terminal; a first p-type transistor having a gate, a first drain-source terminal coupled to the first rail, and a second drain source terminal selectively coupled to the output terminal; a first n-type transistor having a gate, a first drain-source terminal coupled to the second rail, and a second drain source terminal selectively coupled to the output terminal; and repeating-circuit-structure control circuitry. The ring oscillator circuit also includes a voltage supply and control block.

    摘要翻译： 用于测量负偏压温度不稳定效应和/或正偏置温度不稳定效应的环形振荡器电路包括具有第一和第二导轨的环形振荡器和奇数（至少3个）重复电路结构。 每个重复电路结构又包括输入端和输出端; 具有栅极的第一p型晶体管，耦合到第一导轨的第一漏极 - 源极和选择性地耦合到输出端的第二漏极源极; 具有栅极的第一n型晶体管，耦合到第二导轨的第一漏极 - 源极和选择性地耦合到输出端的第二漏极端子; 和重复电路结构控制电路。 环形振荡器电路还包括电压供应和控制块。

    Electronic circuit for measurement of transistor variability and the like
    7.
    发明授权
    Electronic circuit for measurement of transistor variability and the like 有权
    用于测量晶体管变化性的电子电路等

    公开(公告)号：US08004305B2

    公开(公告)日：2011-08-23

    申请号：US12542184

    申请日：2009-08-17

    申请人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    发明人： Keith A. Jenkins ,  Jae-Joon Kim ,  Rahul M. Rao

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2621

    摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.

    摘要翻译： 电子电路包括输出端子和至少第一测量FET。 待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。 第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。 要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。 状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。 状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。 还提供了将输出电压与参考值进行比较的电路。 第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

    Independent-gate controlled asymmetrical memory cell and memory using the cell
    8.
    发明授权
    Independent-gate controlled asymmetrical memory cell and memory using the cell 失效
    独立门控制的非对称存储单元和使用单元的存储器

    公开(公告)号：US07787285B2

    公开(公告)日：2010-08-31

    申请号：US12140366

    申请日：2008-06-17

    申请人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

    发明人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

    摘要翻译： 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 在对应的一个字线结构的控制下，每个非对称单元可以选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

    Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect
    9.
    发明授权
    Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect 有权
    影响NBTI（负偏压温度不稳定）效应和/或PBTI（正偏温度不稳定）效应的电路和设计结构

    公开(公告)号：US07642864B2

    公开(公告)日：2010-01-05

    申请号：US12021459

    申请日：2008-01-29

    申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Tae-Hyoung Kim ,  Pong-Fei Lu ,  Saibal Mukhopadhyay ,  Rahul M. Rao ,  Shao-yi Wang

    发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Tae-Hyoung Kim ,  Pong-Fei Lu ,  Saibal Mukhopadhyay ,  Rahul M. Rao ,  Shao-yi Wang

    IPC分类号： G01R23/00 ,  G01R27/00 ,  G01R27/28 ,  H03B5/24 ,  H03K3/03

    CPC分类号： H03K3/0315

    摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

    摘要翻译： 环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。 所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。 在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。 在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。 还包括类似的基于NAND门的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路 通过门。

    MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME
    10.
    发明申请
    MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME 有权
    具有降低漏电功率的存储器电路和相同的设计结构

    公开(公告)号：US20090251974A1

    公开(公告)日：2009-10-08

    申请号：US12098764

    申请日：2008-04-07

    申请人： Sam Gat-Shang Chu ,  Saiful Islam ,  Jae-Joon Kim ,  Stephen V. Kosonocky

    发明人： Sam Gat-Shang Chu ,  Saiful Islam ,  Jae-Joon Kim ,  Stephen V. Kosonocky

    IPC分类号： G11C7/12 ,  G11C5/14

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/413 ,  G11C2207/2227

    摘要： A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.

    摘要翻译： 存储器电路包括全局读位线，全局读位线锁存器和多个子阵列，每个子阵列包括第一和第二本地读位线，第一和第二本地写位线以及第一和第二多个数组 分别与第一和第二本地读取位线以及第一和第二本地写入位线相互连接的存储器单元。 本地读位线与本地写位线分离。 本地多路复用块与第一和第二本地读位线互连，并且被配置为在断言SLEEP信号时对第一和第二本地读位线进行接地，并且选择性地将本地读位线互连到全局读位线 。 全局复用块与全局读位线互连，并且被配置为在断言SLEEP信号时将全局读位线保持在基本放电状态，并将全局读位线互连到全局读位线锁存器。 还包括所述类型的电路的设计结构。