公开(公告)号：US5440246A

公开(公告)日：1995-08-08

申请号：US216208

申请日：1994-03-22

申请人： Michael A. Murray ,  Li-Chun Li ,  Hsing T. Tuan

发明人： Michael A. Murray ,  Li-Chun Li ,  Hsing T. Tuan

IPC分类号： H03K3/356 ,  H03K19/096

CPC分类号： H03K3/356104

摘要： A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.

摘要翻译： 逻辑锁存器可永久编程为选定状态，用作集成电路中具有极低功耗的控制电路。

公开(公告)号：US5907257A

公开(公告)日：1999-05-25

申请号：US853291

申请日：1997-05-09

申请人： Lawrence Liu ,  Michael A. Murray ,  Li-Chun Li

发明人： Lawrence Liu ,  Michael A. Murray ,  Li-Chun Li

IPC分类号： G05F1/46 ,  G05F1/10

CPC分类号： G05F1/468 ,  G05F1/465

摘要： A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude. The intermediate value reduces the likelihood of latch-up during power-up, but the intermediate value does not go beyond the target value thus does not create a significant pn-junction current leakage in semiconductor regions to which the bias voltage is applied.

摘要翻译： 偏置电压发生器为不同的外部电源电压EVCC产生相同的偏置电压VBB（例如，对于EVCC = 3.3V或5.0V）。 在上电期间，产生VBB的电荷泵由参考EVCC的使能信号ExtEn控制。 之后，内部电源电压IVCC完全发展为独立于EVCC（例如，IVCC = 3.0V）的值，并且电荷泵由参考IVCC的使能信号IntEn控制。 该启用信号IntEn将使VBB达到其目标值，例如-1.5V。 该目标值与EVCC无关。 在上电期间，当电荷泵由ExtEn控制时，偏置电压VBB被驱动到中间值（例如，-0.5V或-1V）。 该中间值取决于EVCC，但是在大小上低于目标值。 中间值降低了在上电期间闭锁的可能性，但是中间值不超过目标值，因此在施加偏置电压的半导体区域中不会产生显着的pn结电流泄漏。

公开(公告)号：US20050036346A1

公开(公告)日：2005-02-17

申请号：US10640928

申请日：2003-08-14

申请人： Youngweon Kim ,  Li-Chun Li

发明人： Youngweon Kim ,  Li-Chun Li

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12

CPC分类号： G11C16/3486 ,  G11C5/147 ,  G11C16/12

摘要： A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

摘要翻译： 诸如闪存EPROM的存储器包括写入电路（58和60），其调整向连接到单元组的存储器单元（50）的写入导体（92）提供多少电流或/和电压，以用于同时写入位 作为这些位中有多少处于一对相反的逻辑状态中的一个的函数的诸如字或字节的位组合到该单元组的单元中。

公开(公告)号：US06777280B2

公开(公告)日：2004-08-17

申请号：US10136498

申请日：2002-04-30

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

公开(公告)号：US06674669B2

公开(公告)日：2004-01-06

申请号：US10268863

申请日：2002-10-09

申请人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

发明人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C8/08

摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

摘要翻译： 在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。 每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。 此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。 如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

公开(公告)号：US06373778B1

公开(公告)日：2002-04-16

申请号：US09493299

申请日：2000-01-28

申请人： Jin Seung Song ,  Li-Chun Li

发明人： Jin Seung Song ,  Li-Chun Li

IPC分类号： G11C800

CPC分类号： G11C7/1027 ,  G11C7/1051 ,  G11C8/10 ,  G11C8/12

摘要： In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

摘要翻译： 在突发操作中，计数器接收一个或多个起始列地址的位。 由计数器产生的计数信号提供给列解码器。 列解码器响应于计数信号的单个值选择两列。 两列可以在非连续的列地址。 或者，两列可以在从奇数列地址边界开始的连续列地址处。 数据在两列和一个缓冲器之间并行传输。 数据在缓冲区和数据终端之间串行传输。 一些实施例适用于由同步动态随机存取存储器的标准定义的突发操作。

公开(公告)号：US06975535B2

公开(公告)日：2005-12-13

申请号：US10640928

申请日：2003-08-14

申请人： Youngweon Kim ,  Li-Chun Li

发明人： Youngweon Kim ,  Li-Chun Li

IPC分类号： G11C5/14 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12

CPC分类号： G11C16/3486 ,  G11C5/147 ,  G11C16/12

摘要： A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

摘要翻译： 诸如闪存EPROM的存储器包括写入电路（58和60），其调整向连接到单元组的存储器单元（50）的写入导体（92）提供多少电流或/和电压，以用于同时写入位 作为这些位中有多少处于一对相反的逻辑状态中的一个的函数的诸如字或字节的位组合到该单元组的单元中。

公开(公告)号：US06757199B2

公开(公告)日：2004-06-29

申请号：US10434262

申请日：2003-05-07

申请人： Hsing Ti Tuan ,  Li-Chun Li

发明人： Hsing Ti Tuan ,  Li-Chun Li

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

摘要翻译： 非易失性存储器阵列可以被扇区擦除，或者可以执行芯片擦除操作以并行地擦除阵列的所有单元。

公开(公告)号：US6133597A

公开(公告)日：2000-10-17

申请号：US900560

申请日：1997-07-25

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

摘要翻译： 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAM和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与另一方面的相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US5889414A

公开(公告)日：1999-03-30

申请号：US840337

申请日：1997-04-28

申请人： Li-Chun Li ,  Lynne Watters ,  Sharlin Fang

发明人： Li-Chun Li ,  Lynne Watters ,  Sharlin Fang

IPC分类号： G11C17/18 ,  G11C29/00 ,  H03K19/173 ,  H03K19/094

CPC分类号： G11C29/88 ,  G11C17/18 ,  G11C29/883 ,  H03K19/1733

摘要： A fuse-programmable circuit controllably enables or disables an electrical signal (S). The circuit includes a transmission gate (118) connected between the circuit's input and output terminals. The transmission gate is controlled by complimentary outputs OUTH, OUTL of a fuse-programmable latch (130). A PMOS transistor (Q41) and a fuse (F41) are connected in series between the output terminal and a power supply voltage (VCC). An NMOS transistor (Q42) and a fuse (F42) are connected in series between the output terminal and a reference voltage (ground). The gate of the PMOS transistor is connected to the latch output OUTH. The gate of the NMOS transistor is connected to the latch output OUTL. When OUTH is high and OUTL is low, the transmission gate couples the signal (S) from the input terminal to the output terminal. When OUTH is low and OUTL is high, the transmission gate is closed. The output terminal is permanently fixed at the power supply voltage level or the reference voltage level depending on which of the two fuses (F41 or F42) is blown and which of the two fuses is intact.

摘要翻译： 熔丝可编程电路可控地启用或禁用电信号（S）。 电路包括连接在电路的输入和输出端子之间的传输门（118）。 传输门由熔丝可编程锁存器（130）的互补输出OUTH，OUTL控制。 PMOS晶体管（Q41）和熔丝（F41）串联连接在输出端子和电源电压（VCC）之间。 NMOS晶体管（Q42）和熔丝（F42）串联在输出端子和参考电压（地）之间。 PMOS晶体管的栅极连接到锁存输出OUTH。 NMOS晶体管的栅极连接到锁存输出OUTL。 当OUTH为高电平且OUTL为低电平时，传输门将信号（S）从输入端子耦合到输出端子。 当OUTH为低电平且OUTL为高电平时，传输门关闭。 输出端子永久固定在电源电压电平或参考电压电平上，这取决于两个保险丝（F41或F42）中的哪一个被熔断，两个保险丝中的哪一个是完整的。