公开(公告)号：US5440246A

公开(公告)日：1995-08-08

申请号：US216208

申请日：1994-03-22

申请人： Michael A. Murray ,  Li-Chun Li ,  Hsing T. Tuan

发明人： Michael A. Murray ,  Li-Chun Li ,  Hsing T. Tuan

IPC分类号： H03K3/356 ,  H03K19/096

CPC分类号： H03K3/356104

摘要： A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.

摘要翻译： 逻辑锁存器可永久编程为选定状态，用作集成电路中具有极低功耗的控制电路。

公开(公告)号：US06674669B2

公开(公告)日：2004-01-06

申请号：US10268863

申请日：2002-10-09

申请人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

发明人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C8/08

摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

摘要翻译： 在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。 每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。 此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。 如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

公开(公告)号：US06584018B2

公开(公告)日：2003-06-24

申请号：US09972388

申请日：2001-10-05

申请人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

发明人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C8/08

摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

公开(公告)号：US5245583A

公开(公告)日：1993-09-14

申请号：US679511

申请日：1991-04-02

申请人： Li-Chun Li ,  Hsing T. Tuan ,  Lynne Hannah

发明人： Li-Chun Li ,  Hsing T. Tuan ,  Lynne Hannah

IPC分类号： G11C8/10 ,  G11C11/408

CPC分类号： G11C8/10 ,  G11C11/4087

摘要： An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; and x-address generator; a y-address generator; a multiplexer circuit for operatively coupling one of the x-address generator and the y-address generator to the address bus; a plurality of y-address decoders each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoders each for producing decoded x-information for at least one of the plurality of x-lines; and a plurality of separate sustain circuits each for sustaining decoded x-information produced by at least one x-decoder.

摘要翻译： 提供一种集成电路存储器件，其包括包括多个存储器核的存储器阵列，每个核心包括存储器单元的二维（x，y）阵列，所述存储器阵列还包括多个x线和多个y 线条 一个地址总线，包括一个以y维取向的第一总线和一个以x维取向的第二总线; 和x地址发生器; 一个y地址生成器; 用于将所述x地址发生器和所述y地址发生器中的一个可操作地耦合到所述地址总线的多路复用器电路; 多个y地址解码器，用于将解码的y信息产生到多个y行中的至少一个; 多个单独的x地址解码器，用于产生所述多个x行中的至少一个的解码的x信息; 以及多个单独的维持电路，用于维持由至少一个x解码器产生的解码的x信息。

公开(公告)号：US5912571A

公开(公告)日：1999-06-15

申请号：US947776

申请日：1997-10-09

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： G11C5/14 ,  G11C8/08 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/22 ,  G11C5/143 ,  G11C8/08 ,  H03K17/223

摘要： A semiconductor device disables itself during power-up until the internal power supply voltage and other circuits reach states in which the device can operate properly. The internal power supply voltage is coupled to the input terminal of an inverter through a delay network. During power-up, the device remains disabled until the voltage at the input terminal of the inverter reaches the inverter trip point. The delay network and the inverter are designed so that the voltage at the inverter's input terminal does not reach the inverter trip point until the internal power supply voltage and other circuits have reached states in which the device can operate properly. When the (device is turned off, the inverter input terminal is discharged quickly by a diode or resistor. Therefore, if the power is turned back on immediately, a suitable delay will be provided.

摘要翻译： 一个半导体器件在上电时会自动关闭，直到内部电源电压和其他电路达到设备可以正常工作的状态。 内部电源电压通过延迟网络耦合到逆变器的输入端。 在上电期间，器件保持禁止，直到变频器输入端的电压到达变频器跳闸点。 延时网络和逆变器的设计使得在内部电源电压和其他电路达到设备正常工作的状态之前，变频器输入端子的电压不会到达变频器跳闸点。 当设备关闭时，变频器输入端子被二极管或电阻器快速放电，因此如果电源立即返回，则会提供适当的延时。

公开(公告)号：US6011737A

公开(公告)日：2000-01-04

申请号：US967436

申请日：1997-11-11

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

摘要翻译： 交错的位线读出放大器架构利用电路来模拟未选择用于连接到激活的存储器单元的每个边沿读出放大器上的存储器单元的影响，从而允许边缘读出放大器与内部的读出放大器同时激活 到存储器阵列，没有烧毁边缘读出放大器的危险。 该结构消除了通常与交错的共享位线读出放大器架构中使用的边缘读出放大器相关联的地址解码电路，从而降低了这种存储器阵列的复杂性并减小了其尺寸。

公开(公告)号：US5838622A

公开(公告)日：1998-11-17

申请号：US850933

申请日：1997-02-28

申请人： Lawrence C. Liu ,  Li-Chun Li ,  Michael A. Murray

发明人： Lawrence C. Liu ,  Li-Chun Li ,  Michael A. Murray

IPC分类号： G11C8/06 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C8/06 ,  G11C11/4082

摘要： A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

摘要翻译： 长X位或长Y位存储在锁存器中，并用于补充非对称DRAM存储器中的Y地址位，从而允许一部分用于需要长X位的设计，并且还用于需要 长Y位

公开(公告)号：US5781488A

公开(公告)日：1998-07-14

申请号：US844541

申请日：1997-04-18

申请人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

发明人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/1051

摘要： In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

摘要翻译： 根据本发明，具有交错位线读出放大器配置的DRAM利用I / O数据路径方案，其使通过I / O数据路径的时间延迟最小化。 DRAM包括第一和第二存储器阵列，其中第一外部读出放大器经由第一列解码电路在输入端子上接收对应于从第一存储器阵列选择的存储器单元的状态的信号。 第二外部读出放大器经由第二列解码电路在输入端子上接收对应于从第二存储器阵列选择的存储器单元的状态的信号。 两个外部读出放大器中的每一个具有一起短接的输出端子。 使用两个外部读出放大器中的每一个的另一个输入端子的三态信号来消除短路输出端子上的数据争用。

公开(公告)号：US5844296A

公开(公告)日：1998-12-01

申请号：US717471

申请日：1996-09-20

申请人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

发明人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

IPC分类号： H01L21/8242 ,  H01L23/525 ,  H01L23/58 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L27/10894 ,  H01L2924/0002

摘要： A compact laser programmable fuse structure has a central line and two sets of fuses extending from opposite sides of the central line. An opening through a passivation layer exposes the fuses and overlies the central line. In one embodiment, the opening also exposes the portions of the central line. The central line is made of fuse material or another material for which the opening does not create reliability problems. In one embodiment of the invention, the central line and the fuses are parts of a single contiguous region of polysilicon. This fuse structure has a length that is about half the length of conventional fuse structure having the same number of fuses because two fuses, one on either side of the central line, fit within a length used for a single fuse in conventional fuse structures.

摘要翻译： 紧凑的激光可编程熔丝结构具有中心线和两组从中心线的相对侧延伸的保险丝。 通过钝化层的开口露出熔丝并覆盖中心线。 在一个实施例中，开口也暴露中心线的部分。 中心线由保险丝材料或其他材料制成，开口不会产生可靠性问题。 在本发明的一个实施例中，中心线和熔丝是多晶硅的单个连续区域的部分。 这种熔丝结构的长度大约是具有相同数量的保险丝的常规熔断器结构的长度的一半，因为两个保险丝（一个位于中心线的任一侧上）都配合在常规保险丝结构中用于单个保险丝的长度内。

公开(公告)号：US5838072A

公开(公告)日：1998-11-17

申请号：US805391

申请日：1997-02-24

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： H01L23/50 ,  H01L23/52 ,  H01L23/28 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L23/52 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/14

摘要： An integrated circuit has a supply node for supplying power to at least one intermediate node coupled to circuitry for receiving power. Rather than transmit power from the supply node to the intermediate node by means of a power bus formed as part of the chip interconnect structure, power is supplied to an external wire which is coupled from the supply to the intermediate node. Other than as connected to the supply node and intermediate node, the wire is electrically isolated from the die. This structure and method for making the semiconductor package allow power to be distributed within a semiconductor chip without sacrificing valuable chip space and without requiring a special lead frame for distributing the power within the semiconductor chip.

摘要翻译： 集成电路具有用于向耦合到用于接收功率的电路的至少一个中间节点供电的供电节点。 不是通过形成为芯片互连结构的一部分的电源总线将功率从供电节点传输到中间节点，而是将电力供应到从电源耦合到中间节点的外部电线。 除了连接到供电节点和中间节点之外，导线与模具电隔离。 用于制造半导体封装的这种结构和方法允许电力分配在半导体芯片内，而不牺牲有价值的芯片空间，而不需要用于在半导体芯片内分配功率的特殊引线框架。