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    STEP SOFT PROGRAM FOR REVERSIBLE RESISTIVITY-SWITCHING ELEMENTS
    12.
    发明申请
    STEP SOFT PROGRAM FOR REVERSIBLE RESISTIVITY-SWITCHING ELEMENTS 有权
    用于可逆电阻开关元件的步骤软件程序

    公开(公告)号：US20110205782A1

    公开(公告)日：2011-08-25

    申请号：US12949146

    申请日：2010-11-18

    申请人： Xiying Chen Costa ,  Roy Scheuerlein ,  Abhijit Bandyopadhyay ,  Brian Le ,  Li Xiao ,  Tao Du ,  Chandrasekhar R. Gorla

    发明人： Xiying Chen Costa ,  Roy Scheuerlein ,  Abhijit Bandyopadhyay ,  Brian Le ,  Li Xiao ,  Tao Du ,  Chandrasekhar R. Gorla

    IPC分类号： G11C11/21

    CPC分类号： G11C14/00 ,  G11C5/02 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/32

    摘要： A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.

    摘要翻译： 公开了一种用于形成，复位或设置存储单元的方法和系统。 可以基于其电阻来确定应用于具有可逆电阻率开关元件的存储单元的一个或多个编程条件。 一个或多个编程条件的确定也可以基于可以基于存储器单元的性质的预定算法。 一个或多个编程条件可以包括编程电压和电流限制。 例如，编程电压的大小可以基于电阻。 作为另一示例，编程电压脉冲的宽度可以基于电阻。 在一些实施例中，基于存储单元电阻来确定在编程期间使用的电流限制。

    NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL
    13.
    发明申请
    NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL 有权
    通过在多晶半导体材料中增加订单来操作非易失性存储器单元

    公开(公告)号：US20120300533A1

    公开(公告)日：2012-11-29

    申请号：US13568834

    申请日：2012-08-07

    申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

    发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

    IPC分类号： G11C11/00 ,  H01L27/26 ,  H01L47/00

    CPC分类号： G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

    摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

    摘要翻译： 提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导​​体和半导体结二极管。 半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。 此外，在半导体结二极管和第一导体之间或半导体结二极管和第二导体之间设置不具有通过施加编程电压大于2的电阻而改变其电阻的电阻切换元件。 提供了许多其他方面。

    Integrated circuit embodying a non-volatile memory cell
    14.
    发明申请
    Integrated circuit embodying a non-volatile memory cell 审中-公开
    集成电路体现了非易失性存储单元

    公开(公告)号：US20070007577A1

    公开(公告)日：2007-01-11

    申请号：US11175688

    申请日：2005-07-06

    申请人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

    发明人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7883 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.

    摘要翻译： 提供了包括至少一个存储单元的集成电路。 这样的存储单元又包括晶体管和电容器。 晶体管包括源极，漏极和栅极。 此外，电容器包括阱和栅极。 晶体管的栅极保持与电容器的栅极通信。 在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。 在这样的实施例中，晶体管的阱邻接电容器的阱。 在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

    3D polysilicon diode with low contact resistance and method for forming same
    17.
    发明授权
    3D polysilicon diode with low contact resistance and method for forming same 有权
    具有低接触电阻的3D多晶硅二极管及其形成方法

    公开(公告)号：US08207064B2

    公开(公告)日：2012-06-26

    申请号：US12562079

    申请日：2009-09-17

    申请人： Abhijit Bandyopadhyay ,  Kun Hou ,  Steven Maxwell

    发明人： Abhijit Bandyopadhyay ,  Kun Hou ,  Steven Maxwell

    IPC分类号： H01L21/44

    CPC分类号： H01L29/868 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/165 ,  H01L29/452 ,  H01L29/456 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

    摘要： A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

    摘要翻译： 半导体p-i-n二极管及其形成方法在此描述。 在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。 在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，其可以在这些二极管与 3D存储器阵列中的R / W材料。

    Highly scalable thin film transistor
    19.
    发明授权
    Highly scalable thin film transistor 有权
    高度可扩展的薄膜晶体管

    公开(公告)号：US07888205B2

    公开(公告)日：2011-02-15

    申请号：US12659480

    申请日：2010-03-10

    申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

    发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11578

    摘要： Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

    摘要翻译： PMOS或NMOS薄膜晶体管的尺寸缩小受掺杂剂扩散的限制。 在这些器件中，未掺杂或轻掺杂的沟道区被插入在重掺杂的源极和漏极区之间。 当器件以非常短的栅极长度构建时，源极和漏极掺杂物将扩散到沟道中，从而潜在地短路并破坏器件。 描述了一组创新，其可以以各种组合使用，以在制造PMOS或NMOS多晶薄膜晶体管期间最小化掺杂剂扩散，导致高度可缩放的薄膜晶体管。 该晶体管特别适用于堆叠器件级的单片三维阵列。

    TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES
    20.
    发明申请
    TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
    用于紧凑的内存阵列的晶体管布局配置

    公开(公告)号：US20060221758A1

    公开(公告)日：2006-10-05

    申请号：US11420787

    申请日：2006-05-29

    申请人： Christopher Petti ,  Roy Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    发明人： Christopher Petti ,  Roy Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    IPC分类号： G11C8/00

    CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

    摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

    摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。 在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。