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11.发明授权Configuring plural cores to perform an instruction having a multi-core characteristic 有权配置多个内核以执行具有多核特性的指令公开(公告)号：US08495342B2
公开(公告)日：2013-07-23
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/30
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译： 具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。 运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。
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12.发明申请Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开基于多处理器目录的一致性协议的功率感知线路干预公开(公告)号：US20090138220A1
公开(公告)日：2009-05-28
申请号：US11946551
申请日：2007-11-28
CPC分类号： G06F12/0817 , Y02D10/13
摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译： 基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。
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13.发明授权Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能公开(公告)号：US07962770B2
公开(公告)日：2011-06-14
申请号：US11960163
申请日：2007-12-19
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译： 提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。 通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为 使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。 通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。
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14.发明授权公开(公告)号：US07870337B2
公开(公告)日：2011-01-11
申请号：US11946249
申请日：2007-11-28
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译： 提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。
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公开(公告)号：US20120002812A1
公开(公告)日：2012-01-05
申请号：US12828080
申请日：2010-06-30
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译： 设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据 由密钥定义的加密顺序。 加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。
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16.发明申请Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能公开(公告)号：US20090164812A1
公开(公告)日：2009-06-25
申请号：US11960163
申请日：2007-12-19
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译： 提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。 通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为 使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。 通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。
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17.发明申请公开(公告)号：US20090138660A1
公开(公告)日：2009-05-28
申请号：US11946249
申请日：2007-11-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1028 , Y02D10/13
摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译： 提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。
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18.发明申请Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions 有权基于执行指令配置核心功能的多核处理器和使用方法公开(公告)号：US20100153700A1
公开(公告)日：2010-06-17
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译： 具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。 运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。
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公开(公告)号：US07930129B2
公开(公告)日：2011-04-19
申请号：US12114032
申请日：2008-05-02
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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公开(公告)号：US09105627B2
公开(公告)日：2015-08-11
申请号：US13289071
申请日：2011-11-04
IPC分类号： H01F5/00 , H01L27/08 , H01L23/498 , H01L23/522 , H01L23/64 , H01L49/02 , H01F17/00 , H01F41/00
CPC分类号： H01L23/49822 , H01F17/0013 , H01F41/005 , H01F2017/0086 , H01L23/5227 , H01L23/645 , H01L28/10 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/01322 , H01L2924/15311 , H01L2924/30107 , H01L2924/00
摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.
摘要翻译： 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。
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