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公开(公告)号：US08835297B2
公开(公告)日：2014-09-16
申请号：US13750606
申请日：2013-01-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Chih-Chieh Cheng , Shih-Guei Yan , Wen-Jer Tsai
IPC: H01L21/3205
CPC classification number: H01L27/11563 , H01L21/28282 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
Abstract: A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer.
Abstract translation: 提供一种用于制造包括以下步骤的非易失性存储器结构的制造方法。 在衬底中形成第一导电型掺杂层。 在基板上形成多个堆叠结构，并且每个堆叠结构都包括电荷存储结构。 在相邻的层叠结构之间的基板上形成第一电介质层。 在相邻的电荷存储结构之间的衬底中形成第二导电型掺杂区。 第二导电型掺杂区域与每个电荷存储结构具有重叠区域。 此外，第二导电型掺杂区域将第一导电类型掺杂层划分成彼此分离的多个第一导电型掺杂区域。 在第一电介质层上形成导电层。
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公开(公告)号：US20250014650A1
公开(公告)日：2025-01-09
申请号：US18474228
申请日：2023-09-26
Applicant: MACRONIX International Co., Ltd.
Inventor： You-Liang Chou , Wen-Jer Tsai , Chih-Chieh Cheng
Abstract: A memory erase method for a memory device and a memory device therefore are provided. The memory device is a 3D NAND flash with high capacity and high performance. The memory erase method includes following steps: providing a memory block, wherein the memory block comprises memory cell strings, the memory cell strings include memory cells, string selection transistors and ground selection transistors; respectively applying corresponding erase voltages to corresponding word lines, a common source line, a corresponding bit line, the string selection transistor and the ground selection transistor of each of the memory cell strings. The voltage difference between a bit line erase voltage and a string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells of the memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit.
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公开(公告)号：US11600339B2
公开(公告)日：2023-03-07
申请号：US17249178
申请日：2021-02-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chih-Chieh Cheng , Chun-Chang Lu , Wen-Jer Tsai
Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.
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公开(公告)号：US11289132B1
公开(公告)日：2022-03-29
申请号：US17168215
申请日：2021-02-05
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hung Huang , Cheng-Hsien Cheng , Chih-Chieh Cheng , Yin-Jen Chen
Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.
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公开(公告)号：US11037632B1
公开(公告)日：2021-06-15
申请号：US16828997
申请日：2020-03-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shaw-Hung Ku , Chih-Chieh Cheng , Cheng-Hsien Cheng , Yu-Hung Huang , Atsuhiro Suzuki , Wen-Jer Tsai
Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.
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Patent Agency Ranking
公开(公告)号：US09349878B2
公开(公告)日：2016-05-24
申请号：US14313614
申请日：2014-06-24
Applicant: MACRONIX International Co., Ltd.
Inventor： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC: H01L29/792 , H01L29/788 , H01L27/115
CPC classification number: H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。
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公开(公告)号：US08981459B2
公开(公告)日：2015-03-17
申请号：US13869300
申请日：2013-04-24
Applicant: MACRONIX International Co., Ltd.
Inventor： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC: H01L29/792 , H01L21/336 , H01L27/115 , H01L21/28
CPC classification number: H01L27/11568 , H01L21/28282 , H01L29/66833 , H01L29/792
Abstract: A semiconductor structure uses its control gate to be the wordline for receiving an operation voltage for the semiconductor structure. The semiconductor structure has a first and a second doped region and a buried channel between the first and the second doped region, wherein the buried channel has a first length along the first direction. The semiconductor structure further has a charge trapping layer stack on the buried channel and a conductive layer on the charge trapping layer stack, wherein the conductive layer extends along the first direction. The conductive layer is configured as both the control gate and the wordline of the semiconductor structure.
Abstract translation: 半导体结构使用其控制栅极作为用于接收半导体结构的工作电压的字线。 半导体结构在第一和第二掺杂区域之间具有第一和第二掺杂区域和掩埋沟道，其中所述掩埋沟道沿着第一方向具有第一长度。 半导体结构还在掩埋沟道上具有电荷俘获层堆叠，并且在电荷俘获层堆叠上具有导电层，其中导电层沿第一方向延伸。 导电层被配置为半导体结构的控制栅极和字线两者。
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公开(公告)号：US20140306282A1
公开(公告)日：2014-10-16
申请号：US14313614
申请日：2014-06-24
Applicant: MACRONIX International Co., Ltd.
Inventor： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC: H01L29/792
CPC classification number: H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
Abstract translation: 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。
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公开(公告)号：US20160218111A1
公开(公告)日：2016-07-28
申请号：US14604134
申请日：2015-01-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Chih-Chieh Cheng , Shih-Guei Yan , Wen-Jer Tsai
IPC: H01L27/115 , G11C16/10 , H01L21/324 , H01L23/528 , H01L21/28 , H01L21/265 , G11C16/04 , G11C16/26
CPC classification number: H01L21/324 , G11C16/10 , G11C16/3427 , H01L27/11565 , H01L27/1157 , H01L29/40117 , H01L2924/0002 , H01L2924/00
Abstract: A memory device is provided. The memory device includes a substrate, a plurality of semiconductor strip structures, a first doped region, a plurality of second doped regions, a plurality of first contacts, and a plurality of second contacts. Each of the semiconductor strip structures extends along a first direction. The first doped region includes a plurality of first portions and a second portion. Each of the first portions is located on a lower part of the corresponding semiconductor strip structure. The second portion is located on a surface of the substrate, and the first portions are connected to the second portion. Each of the second doped regions is located on an upper part of the corresponding semiconductor strip structure. Each of the first contacts is electrically connected to the second portion of the first doped region. Each of the second contacts is electrically connected to the corresponding second doped region.
Abstract translation: 提供存储器件。 存储器件包括衬底，多个半导体条状结构，第一掺杂区，多个第二掺杂区，多个第一触点和多个第二触点。 每个半导体条结构沿着第一方向延伸。 第一掺杂区域包括多个第一部分和第二部分。 每个第一部分位于相应半导体条结构的下部。 第二部分位于基板的表面上，第一部分连接到第二部分。 每个第二掺杂区域位于相应半导体条结构的上部。 每个第一触点电连接到第一掺杂区域的第二部分。 每个第二触点电连接到相应的第二掺杂区域。
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公开(公告)号：US09373629B1
公开(公告)日：2016-06-21
申请号：US14604116
申请日：2015-01-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Shih-Guei Yan , Chih-Chieh Cheng , Wen-Jer Tsai
IPC: H01L27/108 , H01L29/76 , H01L29/94 , H01L31/113 , H01L27/115 , H01L23/535 , H01L21/768
CPC classification number: H01L21/76895 , H01L21/28282 , H01L21/76897 , H01L23/485 , H01L27/11565 , H01L27/1157
Abstract: A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.
Abstract translation: 提供存储器件。 存储器件包括多个堆叠结构，多个第一阶梯式触点和多个第二阶梯触点。 每个堆叠结构在第一方向上延伸，并且包括第一半导体层和第二半导体层。 第二半导体层设置在第一半导体层的上方。 每个第一阶梯式接触件在第二方向上延伸，并且其底表面电连接到第i + 1个堆叠结构和第i + 2个堆叠结构的第一半导体层，其中i是奇数。 每个第二台阶接触件沿第二方向延伸，并且其底表面电连接到第n堆叠结构的第二半导体层和第i + 1个堆叠结构。 第一个方向与第二个方向不同。
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