公开(公告)号：US09455403B1

公开(公告)日：2016-09-27

申请号：US14838500

申请日：2015-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Feng-Min Lee ,  Yu-Yu Lin ,  Dai-Ying Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises an access device, a dielectric layer, a barrier layer, a first interlayer conductor, a first barrier liner, a second interlayer conductor, a second barrier liner, a memory element and a top electrode layer. The access device has two terminals. The dielectric layer covers the access device. The barrier layer is disposed on the dielectric layer. The first and second interlayer conductors are connected to the two terminals, respectively. The first and second barrier liners are disposed on sidewalls of the first and second interlayer conductors, respectively. The memory element is disposed on the first interlayer conductor. The top electrode layer is disposed on the barrier layer and the memory element and covers the memory element.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括存取装置，电介质层，阻挡层，第一层间导体，第一阻挡衬垫，第二层间导体，第二阻挡衬垫，存储元件和顶电极层。 接入设备有两个终端。 电介质层覆盖接入装置。 阻挡层设置在电介质层上。 第一和第二层间导体分别连接到两个端子。 第一和第二阻挡衬垫分别设置在第一和第二层间导体的侧壁上。 存储元件设置在第一层间导体上。 顶部电极层设置在阻挡层和存储元件上并覆盖存储元件。

公开(公告)号：US09455402B2

公开(公告)日：2016-09-27

申请号：US14603390

申请日：2015-01-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Kuang-Hao Chiang ,  Ming-Hsiu Lee

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/04 ,  H01L45/124 ,  H01L45/1633

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Abstract translation: 提供了一种电阻式存储器件，包括底部电极，形成在底部电极上的通孔的图案化电介质层，形成在通孔的侧壁和底部表面的阻挡层作为衬垫，形成在环形金属层 侧壁和阻挡层的底表面，以及形成在环形金属层的顶表面上的环形金属氧化物。

公开(公告)号：US09245925B1

公开(公告)日：2016-01-26

申请号：US14598116

申请日：2015-01-15

Applicant: Macronix International Co., Ltd.

Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Yu-Yu Lin

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming an insulation layer on an access device followed by forming vias through the insulation layer to expose the first and second access device terminals. First and second interlayer conductors extending through the vias are formed next. Top surfaces of the interlayer conductors are oxidized to form oxide layers. The oxide layer on the first interlayer conductor forms a memory layer. On top of the insulation layer a layer of protection metal is formed covering the oxide layers. The layer of protection metal is patterned and etched to form a top electrode layer covering the memory layer. The oxide layer on the second interlayer conductor is removed. Parallel first and second access lines are then formed on the top electrode layer and the second interlayer conductor, respectively.

Abstract translation: 本文描述了基于金属氧化物的存储器件及其制造方法。 一种用于制造存储单元的方法包括在存取装置上形成绝缘层，随后通过绝缘层形成通孔以暴露第一和第二接入装置终端。 接下来形成穿过通孔延伸的第一和第二层间导体。 层间导体的顶表面被氧化形成氧化物层。 第一层间导体上的氧化物层形成存储层。 在绝缘层的顶部，形成覆盖氧化物层的保护金属层。 保护金属层被图案化和蚀刻以形成覆盖存储层的顶部电极层。 去除第二层间导体上的氧化物层。 然后分别在顶电极层和第二层间导体上形成平行的第一和第二存取线。

公开(公告)号：US20240274164A1

公开(公告)日：2024-08-15

申请号：US18166495

申请日：2023-02-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Tian-Cih Bo

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G11C8/08

Abstract: A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.

公开(公告)号：US12040015B2

公开(公告)日：2024-07-16

申请号：US17848521

申请日：2022-06-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C11/419 ,  G06F7/544 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06F7/5443 ,  G11C13/0009 ,  G11C13/0069

Abstract: A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.

公开(公告)号：US11923008B2

公开(公告)日：2024-03-05

申请号：US18155827

申请日：2023-01-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/404 ,  G11C15/04 ,  G11C16/04

CPC classification number: G11C15/04 ,  G11C15/046 ,  G11C11/404 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/4013 ,  G11C2211/4016

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor and a second transistor. Gates of the first and second transistors are coupled to a corresponding first search line and a corresponding second search line.

公开(公告)号：US11871588B2

公开(公告)日：2024-01-09

申请号：US17392365

申请日：2021-08-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Dai-Ying Lee ,  Yu-Hsuan Lin ,  Po-Hao Tseng ,  Ming-Hsiu Lee

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/845 ,  H10B61/22 ,  H10B63/34 ,  H10N50/01 ,  H10N70/066

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

公开(公告)号：US11587623B2

公开(公告)日：2023-02-21

申请号：US17320336

申请日：2021-05-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Yu-Hsuan Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C16/26 ,  G11C16/04 ,  G11C5/06 ,  G11C15/04 ,  G11C16/30

Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.

公开(公告)号：US11557354B2

公开(公告)日：2023-01-17

申请号：US17166484

申请日：2021-02-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  G11C11/56 ,  H01L27/1157

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US20220238151A1

公开(公告)日：2022-07-28

申请号：US17344555

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G06F7/501 ,  G06F7/523

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.