公开(公告)号：US09450577B1

公开(公告)日：2016-09-20

申请号：US14742160

申请日：2015-06-17

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Tzu-Ting Chiu

IPC: H03K3/00 ,  H03K17/16

CPC classification number: H03K19/018507

Abstract: An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.

Abstract translation: 输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。

公开(公告)号：US08922254B2

公开(公告)日：2014-12-30

申请号：US13913139

申请日：2013-06-07

Applicant: Macronix International Co., Ltd.

Inventor： Shang-Chi Yang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/14

CPC classification number: H03K17/145

Abstract: Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.

Abstract translation: 电流驱动器和偏置电路至少部分地补偿制造变化和环境变化，例如电源电压，温度和制造过程。

公开(公告)号：US11894100B2

公开(公告)日：2024-02-06

申请号：US17572674

申请日：2022-01-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh Lo ,  Yi-Fan Chang

IPC: G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/106 ,  G11C7/1057 ,  G11C7/1084

Abstract: A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

公开(公告)号：US11749572B2

公开(公告)日：2023-09-05

申请号：US16877697

申请日：2020-05-19

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/1623

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

公开(公告)号：US11605431B2

公开(公告)日：2023-03-14

申请号：US17325243

申请日：2021-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

公开(公告)号：US10770119B2

公开(公告)日：2020-09-08

申请号：US16534992

申请日：2019-08-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Ming-Chih Hsieh

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06

Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

公开(公告)号：US09419596B2

公开(公告)日：2016-08-16

申请号：US14479104

申请日：2014-09-05

Applicant: Macronix International Co., Ltd.

Inventor： Shang-Chi Yang ,  Su-Chueh Lo

IPC: G05F1/10 ,  H03K5/02 ,  H01L27/06 ,  H01L21/8234

CPC classification number: H03K5/023 ,  G11C7/062 ,  G11C7/12 ,  G11C2207/002 ,  H01L21/8234 ,  H01L27/0617

Abstract: One aspect of the technology is an integrated circuit, comprising a bias circuit and a sense amplifier. The bias circuit has a diode-connected transistor and a first bias voltage. The first bias voltage is represented by a first term inversely dependent on a first mobility of charge carriers of the diode-connected transistor and inversely dependent on a first gate-to-channel dielectric capacitance of the diode-connected transistor. The sense amplifier is coupled to another transistor that has a gate coupled to the first bias voltage of the bias circuit.

Abstract translation: 该技术的一个方面是集成电路，包括偏置电路和读出放大器。 偏置电路具有二极管连接的晶体管和第一偏置电压。 第一偏置电压由与二极管连接的晶体管的电荷载流子的第一迁移率成反比的第一项表示，并且取决于二极管连接晶体管的第一栅极 - 沟道介电电容。 读出放大器耦合到具有与偏置电路的第一偏置电压耦合的栅极的另一个晶体管。

公开(公告)号：US20150023120A1

公开(公告)日：2015-01-22

申请号：US14506768

申请日：2014-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。

公开(公告)号：US20140219026A1

公开(公告)日：2014-08-07

申请号：US14249270

申请日：2014-04-09

Applicant: Macronix International Co., Ltd.

Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC: G11C16/34

CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US20250104750A1

公开(公告)日：2025-03-27

申请号：US18475246

申请日：2023-09-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Yi Cheng ,  Su-Chueh Lo

IPC: G11C7/22 ,  G11C7/10

Abstract: A calibration apparatus of a memory device and a calibration method thereof are provided. The memory device is a 3D NAND flash with high capacity and high performance. The calibration apparatus includes an impedance, a strong-arm comparator, a logic circuit, and a calibration controller. The impedance is configured to generate a comparison voltage. The strong-arm comparator includes a differential input pair and a latch. The differential input pair compares a reference voltage and the comparison voltage to produce a comparison result. The latch latches the comparison result and generates a latch signal and an inverted latch signal accordingly. The logic circuit generates a comparison result signal according to the latch signal and the inverted latch signal. The calibration controller implements an impedance calibration in the memory device according to the comparison result signal.