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    MEMORY DEVICE
    13.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20230290396A1

    公开(公告)日：2023-09-14

    申请号：US18319834

    申请日：2023-05-18

    Applicant: Macronix International Co., Ltd.

    Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

    IPC: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    CPC classification number: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: Provided is a memory device including a stack structure. The stack structure is in the memory array region of a substrate. The stack structure comprises a plurality of first insulating layers and a plurality of conductive layers stacked alternately on each other. A first staircase structure and a second staircase structure are located in a first staircase region and a second staircase region of the substrate respectively. The second staircase structure has steps descending from an upper layer proximal to the memory array region to a lower layer distal to the memory array region. Block slits and zone slit are disposed over the substrate in the second staircase region. The block slits divide the stack structure, the first staircase structure and the second staircase structure into memory blocks. The zone slits divide one of the memory blocks into a plurality of zones separately within the memory blocks.

    Memory device
    15.
    发明授权
    Memory device 有权

    公开(公告)号：US11637125B2

    公开(公告)日：2023-04-25

    申请号：US17075480

    申请日：2020-10-20

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

    Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

    MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    16.
    发明申请
    MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220199134A1

    公开(公告)日：2022-06-23

    申请号：US17131437

    申请日：2020-12-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

    IPC: G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

    Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

    SEMICONDUCTOR MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    18.
    发明申请
    SEMICONDUCTOR MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210351196A1

    公开(公告)日：2021-11-11

    申请号：US16867063

    申请日：2020-05-05

    Applicant: Macronix International Co., Ltd.

    Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/06 ,  G11C5/02

    Abstract: Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

    Semiconductor Devices and Fabrication Methods With Reduced Topology And Reduced Word Line Stringer Residual Material
    20.
    发明申请
    Semiconductor Devices and Fabrication Methods With Reduced Topology And Reduced Word Line Stringer Residual Material 审中-公开
    半导体器件和制造方法具有减少拓扑和减少字线串痕残留材料

    公开(公告)号：US20160020143A1

    公开(公告)日：2016-01-21

    申请号：US14334363

    申请日：2014-07-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L29/66825 ,  H01L27/11521 ,  H01L29/7881

    Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a first dielectric layer over buried oxide regions and the removal of such dielectric layer to prepare a substantially planar substrate for subsequent formation of word lines. The method may allow for the production of semiconductor memory devices of reduced size with reduced word line stringer residual material.

    Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在掩埋氧化物区域上形成第一电介质层，以及去除这种电介质层以制备用于随后形成字线的基本平坦的衬底。 该方法可以允许使用减少的字线纵梁残余材料来生产尺寸减小的半导体存储器件。

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