公开(公告)号：US20200312866A1

公开(公告)日：2020-10-01

申请号：US16371579

申请日：2019-04-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

公开(公告)号：US20180233375A1

公开(公告)日：2018-08-16

申请号：US15955549

申请日：2018-04-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L21/311 ,  H01L23/522 ,  H01L23/485 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/532 ,  H01L23/31 ,  H01L21/28 ,  H01L33/44 ,  H01L31/18

CPC classification number: H01L21/31111 ,  H01L21/28247 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L31/1868 ,  H01L33/44

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

公开(公告)号：US20190214402A1

公开(公告)日：2019-07-11

申请号：US15866132

申请日：2018-01-09

Applicant: MACRONIX International Co., Ltd.

Inventor： I-Ting Lin ,  Yuan-Chieh Chiu ,  Hong-Ji Lee

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L21/28 ,  G11C11/56 ,  G11C16/04 ,  G11C14/00 ,  G11C16/34

CPC classification number: H01L27/11578 ,  G11C11/5671 ,  G11C14/0018 ,  G11C16/0466 ,  G11C16/3422 ,  H01L27/1157 ,  H01L29/40117

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

公开(公告)号：US09953841B2

公开(公告)日：2018-04-24

申请号：US14707648

申请日：2015-05-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L23/532 ,  H01L23/31 ,  H01L21/28 ,  H01L31/18 ,  H01L33/44 ,  H01L21/311 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/31111 ,  H01L21/28247 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L31/1868 ,  H01L33/44

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

公开(公告)号：US20160329243A1

公开(公告)日：2016-11-10

申请号：US14707648

申请日：2015-05-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/28247 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L31/1868 ,  H01L33/44

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 提供基板。 在基板上形成具有开口的材料层。 在开口的侧壁和衬底上形成第一钝化材料层。 对第一钝化材料层进行处理工艺以形成第二钝化材料层。 第二钝化材料层的第一表面和第二钝化材料层的第二表面（在内侧）的性质不同，并且第一表面位于第二钝化材料层的相对远离第二钝化材料层的一侧 材料层。