公开(公告)号：US11211401B2

公开(公告)日：2021-12-28

申请号：US16728394

申请日：2019-12-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20200312866A1

公开(公告)日：2020-10-01

申请号：US16371579

申请日：2019-04-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

公开(公告)号：US10770476B1

公开(公告)日：2020-09-08

申请号：US16371579

申请日：2019-04-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/11568 ,  H01L21/28

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

公开(公告)号：US09825052B2

公开(公告)日：2017-11-21

申请号：US14795689

申请日：2015-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Shih-Ping Hong

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

Abstract: Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

公开(公告)号：US11991882B2

公开(公告)日：2024-05-21

申请号：US17528068

申请日：2021-11-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L29/51

CPC classification number: H10B43/27 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/481 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20220077187A1

公开(公告)日：2022-03-10

申请号：US17528068

申请日：2021-11-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20170053867A1

公开(公告)日：2017-02-23

申请号：US14827971

申请日：2015-08-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Yao-An Chung

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/48 ,  H01L23/528

CPC classification number: H01L23/5222 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract translation: 提供了包括多个第一导电线层，多个支撑结构和电荷存储层的存储器件。 每个第一导电线层沿着由第一方向和第二方向限定的平面延伸。 每个第一导线层包括沿着第一方向延伸的多个第一导电线。 支撑结构位于相邻的第一导线层之间。 电荷存储层覆盖第一导电线的上表面，下表面和两个侧表面以及支撑结构的表面。

公开(公告)号：US09559049B1

公开(公告)日：2017-01-31

申请号：US14827971

申请日：2015-08-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Yao-An Chung

IPC: H01L45/00 ,  H01L43/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/48

CPC classification number: H01L23/5222 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract translation: 提供了包括多个第一导电线层，多个支撑结构和电荷存储层的存储器件。 每个第一导电线层沿着由第一方向和第二方向限定的平面延伸。 每个第一导线层包括沿着第一方向延伸的多个第一导电线。 支撑结构位于相邻的第一导线层之间。 电荷存储层覆盖第一导电线的上表面，下表面和两个侧表面以及支撑结构的表面。

公开(公告)号：US20170011995A1

公开(公告)日：2017-01-12

申请号：US14795689

申请日：2015-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Shih-Ping Hong

IPC: H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

Abstract: Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

Abstract translation: 提供了包括多个位线层和多个支撑结构的存储器件。 每个位线层在由第一方向和第二方向限定的平面中延伸，并且具有沿着第一方向延伸的多个位线。 每个位线具有交替布置的多个宽部分和多个窄部分。 支撑结构设置在相邻位线层的相应位线的宽部分之间。 此外，每个位线的每个窄部分的横截面基本上具有椭圆形形状，并且每个窄部分具有大于约30％的舍入率（RR）。