公开(公告)号：US09905509B2

公开(公告)日：2018-02-27

申请号：US14341351

申请日：2014-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Lu Chen ,  Shih-Ping Hong ,  Ta Hung Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

公开(公告)号：US09825052B2

公开(公告)日：2017-11-21

申请号：US14795689

申请日：2015-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Shih-Ping Hong

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

Abstract: Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

公开(公告)号：US20180233375A1

公开(公告)日：2018-08-16

申请号：US15955549

申请日：2018-04-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L21/311 ,  H01L23/522 ,  H01L23/485 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/532 ,  H01L23/31 ,  H01L21/28 ,  H01L33/44 ,  H01L31/18

CPC classification number: H01L21/31111 ,  H01L21/28247 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L31/1868 ,  H01L33/44

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

公开(公告)号：US09418939B2

公开(公告)日：2016-08-16

申请号：US14539368

申请日：2014-11-12

Applicant: Macronix International Co., Ltd.

Inventor： Ming-Tsung Wu ,  Shih-Ping Hong

IPC: H01L29/788 ,  H01L23/535 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A NAND-based non-volatile memory contact structure includes a trench located adjacent to layered alternating conducting and insulating layers, the layers lining sides and bottom of the trench. A portion of the trench is removed to expose a surface in which electrical connections to the conducting layers are provided on one level.

Abstract translation: 基于NAND的非易失性存储器接触结构包括位于邻近分层交替导电和绝缘层的沟槽，所述层衬在沟槽的侧面和底部。 去除沟槽的一部分以暴露其中在一个层面上提供与导电层的电连接的表面。

公开(公告)号：US10607848B2

公开(公告)日：2020-03-31

申请号：US15955549

申请日：2018-04-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L21/311 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/532 ,  H01L23/31 ,  H01L21/28 ,  H01L33/44 ,  H01L31/18

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

公开(公告)号：US20160197092A1

公开(公告)日：2016-07-07

申请号：US14590081

申请日：2015-01-06

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Ping Hong

IPC: H01L27/115 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L29/0676 ,  H01L29/42392

Abstract: A vertical semiconductor memory device having conducting and charge-trapping columns separated by columns of holes is disclosed. The columns are formed in layers of alternating conducting and insulating material with the conducting/charge-trapping columns and columns of holes separating layers of conducting material into disjoint strips. The conducting columns and separated layers of conducting material form wordlines and bitlines in the device.

Abstract translation: 公开了一种垂直半导体存储器件，其具有由柱列隔开的导电和电荷捕获柱。 这些列以交替导电和绝缘材料的层形成，其中导电/电荷捕获柱和将导电材料层分隔成不相连的条的孔。 导电柱和分离的导电材料层在器件中形成字线和位线。

公开(公告)号：US20160027729A1

公开(公告)日：2016-01-28

申请号：US14341351

申请日：2014-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Lu Chen ,  Shih-Ping Hong ,  Ta Hung Yang

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

Abstract translation: 半导体互连结构形成为具有倒T形的通孔，以增加互连结构和下面的导电（例如铜（Cu））材料层之间的界面的可靠性。 倒T形有效地增加了通孔的底部临界尺寸，从而通过在高温或应力迁移烘烤期间导入的导电层中的空隙引起的互连结构的降解和/或消除。

公开(公告)号：US20150311218A1

公开(公告)日：2015-10-29

申请号：US14259771

申请日：2014-04-23

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Shih-Ping Hong ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/00 ,  H01L29/49

CPC classification number: H01L23/564 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract translation: 描述了一种促进集成电路的密集配置的阵列中的晶体管之间的层间电介质填充的方法。 公开了利用微载荷效应在晶体管之间产生T形轮廓的蚀刻工艺。 微载物对集成电路的外围区域中的晶体管具有可忽略的影响。

公开(公告)号：US09953841B2

公开(公告)日：2018-04-24

申请号：US14707648

申请日：2015-05-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L23/532 ,  H01L23/31 ,  H01L21/28 ,  H01L31/18 ,  H01L33/44 ,  H01L21/311 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/31111 ,  H01L21/28247 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L31/1868 ,  H01L33/44

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

公开(公告)号：US09589979B2

公开(公告)日：2017-03-07

申请号：US14548252

申请日：2014-11-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Ping Hong

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11578 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/511

Abstract: A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures.

Abstract translation: 描述了一种存储器件，其包括一组存储器单元，该存储器单元包括多个水平有源线的堆叠，例如NAND串通道线，多个垂直切片穿过并围绕水平有源线，以提供栅极 - 全方位的结构。 存储膜设置在多个堆叠中的水平有源线和多个垂直片中的垂直片之间。 提供了3D，水平通道，全栅NAND闪存。 存储器的制造方法包括支撑工艺。 支撑过程支持水平通道，闸门全能结构。