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公开(公告)号：US20250013489A1
公开(公告)日：2025-01-09
申请号：US18347643
申请日：2023-07-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Omri Kahalon , Avi Urman , Omer Cohen , Ilan Pardo
IPC: G06F9/48
Abstract: In one embodiment, a network device includes a network interface to receive first packets from a network and send second packets over the network, and packet processing hardware to process a packet, accelerate activation of a given software program by performing at least one activation task of the given software program in hardware, and generate an interrupt to request a processing unit to execute the given software program to perform processing associated with the packet, and the processing unit to execute the given software program and perform processing associated with the packet, responsively to the at least one activation task performed by the packet processing hardware.
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公开(公告)号：US12147855B2
公开(公告)日：2024-11-19
申请号：US17709475
申请日：2022-03-31
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ilan Pardo , Evgeny Pimenov
Abstract: A processor includes a memory and a processing core. The processing core is configured to define, in the memory, a jump table that is indexed by a service identifier and includes start addresses for respective service identifier values, to receive a system call that specifies a service identifier value, and to serve the system call by executing program code starting from a start address corresponding to the specified service identifier value.
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公开(公告)号：US20240202315A1
公开(公告)日：2024-06-20
申请号：US18084964
申请日：2022-12-20
Applicant: Mellanox Technologies, Ltd.
Inventor： Ahmad Atamli , Ilan Pardo , Miriam Menes , Shahaf Shuler , Meni Orenbach , Uria Basher
IPC: G06F21/53
CPC classification number: G06F21/53 , G06F2221/033
Abstract: The technology disclosed herein enables selective clearing of memory regions upon a context switch. An example method includes the operations of: receiving a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.
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公开(公告)号：US20230315547A1
公开(公告)日：2023-10-05
申请号：US17709475
申请日：2022-03-31
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ilan Pardo , Evgeny Pimenov
Abstract: A processor includes a memory and a processing core. The processing core is configured to define, in the memory, a jump table that is indexed by a service identifier and includes start addresses for respective service identifier values, to receive a system call that specifies a service identifier value, and to serve the system call by executing program code starting from a start address corresponding to the specified service identifier value.
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公开(公告)号：US20230315457A1
公开(公告)日：2023-10-05
申请号：US17709464
申请日：2022-03-31
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ilan Pardo , Evgeny Pimenov
CPC classification number: G06F9/30145 , G06F9/30105 , G06F1/08
Abstract: A processor includes a set of registers and a processing core. The processing core is configured to execute instructions, including an instruction that causes the core to reset a plurality of the registers in the set.
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Patent Agency Ranking
公开(公告)号：US20230010161A1
公开(公告)日：2023-01-12
申请号：US17369992
申请日：2021-07-08
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ilan Pardo
IPC: H04L12/863 , H04L12/861
Abstract: A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.
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公开(公告)号：US20220350756A1
公开(公告)日：2022-11-03
申请号：US17306033
申请日：2021-05-03
Applicant: Mellanox Technologies LTD.
Inventor： Idan Burstein , Ilan Pardo , Yamin Friedman , Michael Cotsford , Mark Rosenbluth , Hillel Chapman
Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.
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公开(公告)号：US10394747B1
公开(公告)日：2019-08-27
申请号：US15609433
申请日：2017-05-31
Applicant: Mellanox Technologies, Ltd.
Inventor： Peter Paneah , Carl G. Ramey , Gil Moran , Adi Menachem , Christopher J. Jackson , Ilan Pardo , Ariel Shahar , Tzuriel Katoa
Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.
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公开(公告)号：US12259963B2
公开(公告)日：2025-03-25
申请号：US17676890
申请日：2022-02-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Boris Pismenny , Miriam Menes , Ahmad Atamli , Ilan Pardo , Ariel Shahar , Uria Basher
Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.
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公开(公告)号：US11762785B2
公开(公告)日：2023-09-19
申请号：US17306033
申请日：2021-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Idan Burstein , Ilan Pardo , Yamin Friedman , Michael Cotsford , Mark Rosenbluth , Hillel Chapman
CPC classification number: G06F13/1668 , G06F12/0246 , G06F12/0811 , G06F13/382 , G06F13/4221 , G06F15/7807 , G06F2213/0026
Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.
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