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    FIXED VOLTAGE SENSING IN A MEMORY DEVICE
    11.
    发明申请
    FIXED VOLTAGE SENSING IN A MEMORY DEVICE 有权
    在存储器件中固定电压传感

    公开(公告)号：US20160035406A1

    公开(公告)日：2016-02-04

    申请号：US14451071

    申请日：2014-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Adam D. Johnson

    IPC: G11C11/22

    CPC classification number: G11C11/2273

    Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

    Abstract translation: 已经公开了用于感测铁电存储器件的方法和使用其的装置。 一种这样的装置包括耦合到数据线，参考电容和耦合在数据线和参考电容之间的公共节点的铁电存储单元。 电流镜电路耦合到数据线和参考电容。 在感测操作期间，公共节点被配置为处于固定电压，并且电流镜电路被配置为将来自参考电容的位移电流镜像到铁电存储器单元。

    RESISTIVE MEMORY SENSING
    12.
    发明申请
    RESISTIVE MEMORY SENSING 审中-公开
    电阻记忆感应

    公开(公告)号：US20150255153A1

    公开(公告)日：2015-09-10

    申请号：US14719053

    申请日：2015-05-21

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

    Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

    APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING
    13.
    发明申请
    APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING 有权
    用于形成使用充电监测的存储器单元的装置和方法

    公开(公告)号：US20150124517A1

    公开(公告)日：2015-05-07

    申请号：US14588593

    申请日：2015-01-02

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Durai Vishak Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Adam D. Johnson ,  Scott E. Sills ,  Alessandro Calderoni

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  H01L22/14

    Abstract: Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

    Abstract translation: 描述形成存储器单元的装置和方法。 在一种这样的方法中，监视施加到诸如电阻RAM（RRAM）存储单元的存储单元的成形电荷，以确定形成单元的进程。 如果电池消耗电荷太慢，则可以施加更高的电压。 如果电池消耗电荷太快，则可以施加较低的电压。 可以通过将电容器充电到一定水平来监测电荷，然后通过电池监测电容器的放电速率。 监控可以使用比较器来测量电荷。 监视还可以使用模数转换器来执行监视。

    APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING
    15.
    发明申请
    APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING 有权
    用于形成使用充电监测的存储器单元的装置和方法

    公开(公告)号：US20140233298A1

    公开(公告)日：2014-08-21

    申请号：US13772056

    申请日：2013-02-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Brent Keeth ,  Durai Vishak Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Adam D. Johnson ,  Scott E. Sills ,  Alessandro Calderoni

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  H01L22/14

    Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

    Abstract translation: 描述形成存储器单元的装置和方法。 在一种这样的方法中，监视施加到诸如电阻RAM（RRAM）存储单元的存储单元的成形电荷，以确定形成单元的进程。 如果电池消耗电荷太慢，则可以施加更高的电压。 如果电池消耗电荷太快，则可以施加较低的电压。 可以通过将电容器充电到一定水平来监测电荷，然后通过电池监测电容器的放电速率。 监控可以使用比较器来测量电荷。 监视还可以使用模数转换器来执行监视。

    Fixed voltage sensing in a memory device
    16.
    发明授权
    Fixed voltage sensing in a memory device 有权

    公开(公告)号：US10770125B2

    公开(公告)日：2020-09-08

    申请号：US15415611

    申请日：2017-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Adam D. Johnson

    IPC: G11C11/22

    Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.

    MITIGATING DISTURBANCES OF MEMORY CELLS
    17.
    发明申请
    MITIGATING DISTURBANCES OF MEMORY CELLS 审中-公开

    公开(公告)号：US20190043595A1

    公开(公告)日：2019-02-07

    申请号：US15669785

    申请日：2017-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Vimercati ,  Mark Fischer ,  Adam D. Johnson

    IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56

    CPC classification number: G11C16/3427 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

    Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

    APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD
    19.
    发明申请
    APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD 审中-公开

    公开(公告)号：US20170358599A1

    公开(公告)日：2017-12-14

    申请号：US15688260

    申请日：2017-08-28

    Applicant: Micron Technology, Inc.

    Inventor： D.V. Nirmal Ramaswamy ,  Adam D. Johnson

    IPC: H01L27/11597 ,  H01L29/78 ,  G11C11/22

    CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

    Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

    Apparatuses having a ferroelectric field-effect transistor memory array and related method
    20.
    发明授权
    Apparatuses having a ferroelectric field-effect transistor memory array and related method 有权

    公开(公告)号：US09786684B2

    公开(公告)日：2017-10-10

    申请号：US15379933

    申请日：2016-12-15

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Adam D. Johnson

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L29/78

    CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

    Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

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