公开(公告)号：US20250166993A1

公开(公告)日：2025-05-22

申请号：US19026037

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L21/027 ,  B81C1/00 ,  B82Y40/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming a nanostructure comprises forming an initial pattern of self-assembled nucleic acids on a substrate. The initial pattern of self-assembled nucleic acid exhibits at least one defect. The initial pattern of self-assembled nucleic acids is contacted with at least one enzyme to repair the at least one defect and form a reduced defect pattern of self-assembled nucleic acids. The method also includes transferring the reduced defect pattern of self-assembled nucleic acids to the substrate to form a patterned substrate. At least one dimension of the pattern on the patterned substrate is less than about 50 nanometers (nm). Additional methods are also disclosed.

公开(公告)号：US20240339543A1

公开(公告)日：2024-10-10

申请号：US18743686

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Witold Kula ,  Gurtej S. Sandhu ,  John A. Smythe

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H10B99/00

CPC classification number: H01L29/78642 ,  H01L21/02178 ,  H01L21/02488 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78645 ,  H01L29/78696 ,  H10B99/00 ,  H01L21/0262

Abstract: An apparatus including an array of memory cells comprising transistors is disclosed. One or more of the transistors comprise a crystalline material extending substantially transverse to a base material. A gate dielectric material is adjacent to the crystalline material. A two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. The gate dielectric material overlies additional portions of the two-dimensional material of the channel region. One or more gates are adjacent to the gate dielectric material. An electronic device is also disclosed comprising one or more of the transistors. The one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. The channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.

公开(公告)号：US12052863B2

公开(公告)日：2024-07-30

申请号：US16572926

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B99/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B99/00

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

公开(公告)号：US11882685B2

公开(公告)日：2024-01-23

申请号：US17338195

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L29/78 ,  H10B12/00 ,  H01L21/8254 ,  H01L49/02

CPC classification number: H10B12/30 ,  H01L21/8254 ,  H01L28/60 ,  H10B12/03 ,  H10B12/05 ,  H10B12/053

Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

公开(公告)号：US11631697B2

公开(公告)日：2023-04-18

申请号：US17672659

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11600485B2

公开(公告)日：2023-03-07

申请号：US17186282

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Matthew S. Thorum ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L21/677 ,  H01L21/311 ,  H01L21/67

Abstract: In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

公开(公告)号：US11515198B2

公开(公告)日：2022-11-29

申请号：US16941311

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Scott L. Light ,  John A. Smythe ,  Sony Varghese

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/06 ,  G03F7/075 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  G03F7/30 ,  G03F7/023 ,  H01L21/311

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation. Subsequently, the photopatternable dielectric material is developed to pattern the photopatternable dielectric material into a first dielectric structure which at least partially fills the opening, and to remove the photopatternable dielectric material from over the upper surface.

公开(公告)号：US20220223602A1

公开(公告)日：2022-07-14

申请号：US17705680

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe, III

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

公开(公告)号：US20220173123A1

公开(公告)日：2022-06-02

申请号：US17672659

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220158086A1

公开(公告)日：2022-05-19

申请号：US17649771

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attractor species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attractor species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.