公开(公告)号：US09047191B2

公开(公告)日：2015-06-02

申请号：US14151442

申请日：2014-01-09

Applicant: Micron Technology, Inc.

Inventor： Christopher Bueb ,  Sean Eilert

IPC: H03M13/00 ,  G06F11/07 ,  G06F11/10 ,  H03M13/13 ,  H03M13/37

CPC classification number: G06F11/1076 ,  G06F11/0793 ,  G06F11/1012 ,  H03M13/13 ,  H03M13/159 ,  H03M13/3746 ,  H03M13/6325

Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

Abstract translation: 一种方法包括：计算在第一组条件下从存储器位置读取的码字的第一校正子，并计算在第二组条件下从存储器位置读取的码字的第二校正子。 该方法还包括分析第一和第二校正子并将第一和第二校正子中的一个应用于码字以找到具有最小错误数的码字。

公开(公告)号：US20150095742A1

公开(公告)日：2015-04-02

申请号：US14511102

申请日：2014-10-09

Applicant: Micron Technology, Inc.

Inventor： Christopher Bueb

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G11C29/52

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，多个比特可以通过对多个比特的比特的多个多级存储器单元的子集进行电平移位来编码到多个存储器单元中。 可以描述和要求保护其他实施例。

公开(公告)号：US20140173383A1

公开(公告)日：2014-06-19

申请号：US14187086

申请日：2014-02-21

Applicant: Micron Technology, Inc.

Inventor： Christopher Bueb

IPC: G06F11/10

CPC classification number: G06F11/1072 ,  G11C29/52

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以通过改变多个存储单元的相应组的存储单元的逻辑电平来响应多个比特中的比特来将多个比特编码成多个存储单元。 可以描述和要求保护其他实施例。

公开(公告)号：US20140129872A1

公开(公告)日：2014-05-08

申请号：US14151442

申请日：2014-01-09

Applicant: Micron Technology, Inc.

Inventor： Christopher Bueb ,  Sean Eilert

IPC: G06F11/07

CPC classification number: G06F11/1076 ,  G06F11/0793 ,  G06F11/1012 ,  H03M13/13 ,  H03M13/159 ,  H03M13/3746 ,  H03M13/6325

Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

Abstract translation: 一种方法包括：计算在第一组条件下从存储器位置读取的码字的第一校正子，并计算在第二组条件下从存储器位置读取的码字的第二校正子。 该方法还包括分析第一和第二校正子并将第一和第二校正子中的一个应用于码字以找到具有最小错误数的码字。

公开(公告)号：US20130080856A1

公开(公告)日：2013-03-28

申请号：US13684919

申请日：2012-11-26

Applicant: Micron Technology, Inc.

Inventor： Christopher Bueb

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048 ,  G06F11/1068

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例提供了与具有扩展的纠错保护的NVM设备相关的方法和装置。 在一些实施例中，奇偶校验高速缓存用于存储存储在NVM设备的多个码字中的数据值的奇偶校验值。 可以描述和要求保护其他实施例。

公开(公告)号：US20210117338A1

公开(公告)日：2021-04-22

申请号：US16658971

申请日：2019-10-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Bueb ,  Poorna Kale

IPC: G06F12/126 ,  G06F12/02 ,  G06F11/30 ,  G11C11/409 ,  G11C11/56

Abstract: A priority for each operating requirement of a set of operating requirements of a memory sub-system can be determined. A programming operation setting for a programming operation to be performed at the memory sub-system can be determined based on the priority for each operating requirement. A request to perform the programming operation at the memory sub-system can be received. Responsive to receiving the request to perform the programming operation, the programming operation can be performed at the memory sub-system based on the programming operation setting.

公开(公告)号：US20200058327A1

公开(公告)日：2020-02-20

申请号：US16518651

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Tyson M. Stichka ,  Preston Allen Thomson ,  Scott Anthony Stoller ,  Christopher Bueb ,  Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi

IPC: G11C5/00 ,  G11C7/04 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C7/10

Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

公开(公告)号：US10432230B2

公开(公告)日：2019-10-01

申请号：US13959308

申请日：2013-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Bueb ,  Sean Eilert

IPC: H03M13/29 ,  H03M13/09

Abstract: Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.

公开(公告)号：US10360947B2

公开(公告)日：2019-07-23

申请号：US15692508

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Tyson M. Stichka ,  Preston Thomson ,  Scott Anthony Stoller ,  Christopher Bueb ,  Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Singidi

IPC: G11C16/06 ,  G11C5/00 ,  G11C16/26 ,  G11C16/04 ,  G11C7/04

Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

公开(公告)号：US08887028B2

公开(公告)日：2014-11-11

申请号：US14187086

申请日：2014-02-21

Applicant: Micron Technology, Inc.

Inventor： Christopher Bueb

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1072 ,  G11C29/52

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed.