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    Apparatuses and methods for die seal crack detection
    12.
    发明授权
    Apparatuses and methods for die seal crack detection 有权
    模具密封裂纹检测的装置和方法

    公开(公告)号：US09287184B2

    公开(公告)日：2016-03-15

    申请号：US14106190

    申请日：2013-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

    IPC: H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L29/78

    CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

    Abstract translation: 设备和方法可以包括在管芯的集成电路区域和管芯周边之间的管芯密封。 通孔链可围绕模具密封件和集成电路区域之间的模具密封件的内圆周和/或围绕模具密封件和模具周边之间的模具密封件的外圆周布置。 通孔链可以包括多个由导电材料组成并且延伸穿过模具的部分的触点。 电路可以耦合到通孔链的端部以检测电信号。 描述附加的装置和方法。

    3-D memory arrays
    16.
    发明授权
    3-D memory arrays 有权
    3-D存储器阵列

    公开(公告)号：US09219070B2

    公开(公告)日：2015-12-22

    申请号：US13759627

    申请日：2013-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Deepak Thimmegowda ,  Brian Cleereman ,  Khaled Hasnat

    IPC: H01L29/41 ,  H01L29/417 ,  H01L27/115 ,  H01L27/02 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

    Abstract translation: 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，该栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。

    APPARATUSES AND METHODS FOR DIE SEAL CRACK DETECTION
    17.
    发明申请
    APPARATUSES AND METHODS FOR DIE SEAL CRACK DETECTION 有权
    DIE密封破裂检测的装置和方法

    公开(公告)号：US20150170979A1

    公开(公告)日：2015-06-18

    申请号：US14106190

    申请日：2013-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

    IPC: H01L21/66

    CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

    Abstract translation: 设备和方法可以包括在管芯的集成电路区域和管芯周边之间的管芯密封。 通孔链可围绕模具密封件和集成电路区域之间的模具密封件的内圆周和/或围绕模具密封件和模具周边之间的模具密封件的外圆周布置。 通孔链可以包括多个由导电材料组成并且延伸穿过模具的部分的触点。 电路可以耦合到通孔链的端部以检测电信号。 描述附加的装置和方法。

    MEMORY DEVICES AND RELATED METHODS
    20.
    发明申请
    MEMORY DEVICES AND RELATED METHODS 审中-公开

    公开(公告)号：US20190237362A1

    公开(公告)日：2019-08-01

    申请号：US16377883

    申请日：2019-04-08

    Applicant: Micron Technology, Inc.

    Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

    IPC: H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11519 ,  H01L21/033 ,  H01L23/535 ,  H01L21/3213 ,  H01L27/105

    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

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