公开(公告)号：US20240289218A1

公开(公告)日：2024-08-29

申请号：US18586048

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： David Ebsen ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Dung V. Nguyen ,  Kevin R. Brandt ,  Vikas Rana ,  William Richard Akin

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F13/1673

Abstract: Data is read from a set of memory cells of a memory device to a buffer of the memory device. One or more bits in error in the data stored by the buffer are corrected by a decoder of the memory device. The decoder corrects the one or more bits in error by decoding the data stored by the buffer. The decoding of the data results in corrected data. An encoder of the memory device encodes the corrected data and the encoded corrected data is programmed to the set of memory cells.

公开(公告)号：US20240087651A1

公开(公告)日：2024-03-14

申请号：US17941831

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Akira Goda ,  Dung V. Nguyen ,  Giovanni Maria Paolucci ,  James Fitzpatrick ,  Eric N. Lee ,  Dave Scott Ebsen ,  Tomoharu Tanaka

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/32

Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

公开(公告)号：US20240028252A1

公开(公告)日：2024-01-25

申请号：US17872426

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Dung V. Nguyen ,  Dave Scott Ebsen ,  Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Akira Goda ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

公开(公告)号：US20220392500A1

公开(公告)日：2022-12-08

申请号：US17342171

申请日：2021-06-08

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen

IPC: G11C7/10 ,  H03K23/00 ,  H03K19/20

Abstract: A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.

公开(公告)号：US20220253354A1

公开(公告)日：2022-08-11

申请号：US17540059

申请日：2021-12-01

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen ,  Sivagnanam Parthasarathy

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15

Abstract: Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.

公开(公告)号：US12249364B2

公开(公告)日：2025-03-11

申请号：US17890040

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Akira Goda ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Tomoharu Tanaka ,  Eric N. Lee ,  Dung V. Nguyen ,  David Ebsen

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

公开(公告)号：US11960722B2

公开(公告)日：2024-04-16

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20240062799A1

公开(公告)日：2024-02-22

申请号：US17890040

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Akira Goda ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Tomoharu Tanaka ,  Eric N. Lee ,  Dung V. Nguyen ,  David Ebsen

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/4085

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

公开(公告)号：US20240028200A1

公开(公告)日：2024-01-25

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US11663079B2

公开(公告)日：2023-05-30

申请号：US17540059

申请日：2021-12-01

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen ,  Sivagnanam Parthasarathy

IPC: G06F11/10 ,  H03M13/15 ,  G06F11/07

CPC classification number: G06F11/1076 ,  G06F11/076 ,  G06F11/0772 ,  H03M13/1575

Abstract: Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.