公开(公告)号：US10600473B2

公开(公告)日：2020-03-24

申请号：US16549554

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US10402116B2

公开(公告)日：2019-09-03

申请号：US15837685

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072 ,  G11C29/52 ,  G06F11/10

Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US20190131308A1

公开(公告)日：2019-05-02

申请号：US15802016

申请日：2017-11-02

Applicant: Micron Technology, Inc.

Inventor： Mansour Fardad ,  Harish N. Venkata ,  Jeffrey Koelling

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4072 ,  G11C29/12

Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

公开(公告)号：US20180114551A1

公开(公告)日：2018-04-26

申请号：US15797759

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/005 ,  H03K19/20

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US20180108397A1

公开(公告)日：2018-04-19

申请号：US15292941

申请日：2016-10-13

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US09767864B1

公开(公告)日：2017-09-19

申请号：US15216256

申请日：2016-07-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/222 ,  G11C8/10 ,  G11C11/403 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US20160071556A1

公开(公告)日：2016-03-10

申请号：US14944622

申请日：2015-11-18

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  John F. Schreck ,  Mansour Fardad

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract translation: 公开了与具有单独的全局读写线和/或读出放大器区域列选择线的存储器阵列相关的装置和方法。 示例性装置包括第一和第二存储器部分，并且还包括读出放大器区域。 存储器部分包括在第一方向上延伸的字线和在第二方向上延伸的数字线，并且读出放大器区域设置在第一和第二存储器部分之间。 感测放大器区域包括耦合到数字线的读出放大器，本地输入/输出（LIO）线，耦合到读出放大器的列选择电路和列选择线。 列选择线在第一方向上延伸并且被配置为向列选择电路提供列选择信号。 LIO线的电容可以通过将较少的组的读出放大器耦合到LIO线来减少。

公开(公告)号：US20210056045A1

公开(公告)日：2021-02-25

申请号：US16545949

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata

IPC: G06F12/14 ,  G11C11/406 ,  G11C11/409 ,  G06F13/16 ,  G11C11/4074

Abstract: Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

公开(公告)号：US10854247B2

公开(公告)日：2020-12-01

申请号：US16537775

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  H03K19/20 ,  G11C7/08 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US20200219553A1

公开(公告)日：2020-07-09

申请号：US16827044

申请日：2020-03-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.