公开(公告)号：US09747048B2

公开(公告)日：2017-08-29

申请号：US14724473

申请日：2015-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: H04L1/18 ,  G06F3/06 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873 ,  G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G06F13/38 ,  G06F13/16

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/10 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F13/16 ,  G06F13/38 ,  G11C29/52 ,  H04L1/189 ,  H04L47/12 ,  H04L47/25 ,  H04L47/52 ,  Y02D10/14

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

公开(公告)号：US09733847B2

公开(公告)日：2017-08-15

申请号：US14724446

申请日：2015-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F12/00 ,  G06F3/06 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873 ,  G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  H04L1/18 ,  G06F13/38

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/10 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F13/16 ,  G06F13/38 ,  G11C29/52 ,  H04L1/189 ,  H04L47/12 ,  H04L47/25 ,  H04L47/52 ,  Y02D10/14

Abstract: A memory device includes a memory component that store data and a processor. The processor may generate one or more data packets associated with the memory component. Each data packet may include a transaction type field that includes data indicative of a first size of a payload of the respective data packet and a second size of an error control code in the respective data packet. Each packet may also have a payload field that includes the payload and an error control code field that includes the error control code. The processor may transmit the data packets to a requesting component, such that the requesting component identifies the payload field and the error control field of each data packet based on the data of the transaction type field in each data packet.

公开(公告)号：US09633713B2

公开(公告)日：2017-04-25

申请号：US15063140

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC: G11C5/14 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4076 ,  G11C7/10 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands.

公开(公告)号：US09286161B2

公开(公告)日：2016-03-15

申请号：US14464865

申请日：2014-08-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  G11C11/406 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

公开(公告)号：US20150347226A1

公开(公告)日：2015-12-03

申请号：US14724473

申请日：2015-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F11/10 ,  H04L1/18

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/10 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F13/16 ,  G06F13/38 ,  G11C29/52 ,  H04L1/189 ,  H04L47/12 ,  H04L47/25 ,  H04L47/52 ,  Y02D10/14

Abstract: A memory device includes a memory component that store data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

Abstract translation: 存储器设备包括存储数据的存储器组件和处理器。 处理器可以从请求组件接收执行多个数据操作的请求，生成与多个数据操作相关联的多个分组，并且连续发送多个分组中的每一个，直到发送多个分组中的每一个。 在多个分组的第一分组之后的多个分组中的每一个在紧接在先前分组被发送之后的随后的时钟周期上被发送。

公开(公告)号：US20140156948A1

公开(公告)日：2014-06-05

申请号：US13692907

申请日：2012-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Roberts ,  J. Thomas Pawlowski

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/283 ,  G06F2212/602 ,  Y02D10/13

Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

Abstract translation: 描述用于高速缓冲存储器的装置和方法。 在示例性方法中，引用与高速缓存块相关联的事务历史，并且从存储器读取所请求的信息。 基于事务历史从存储器读取附加信息，其中从存储器一起读取所请求的信息和附加信息。 请求的信息被缓存在高速缓存块的高速缓存行的段中，并且缓存在高速缓存行的另一段中的附加信息。 在另一个示例中，交易历史也被更新以反映所请求信息和附加信息的缓存。 在另一示例中，对于事务历史引用与高速缓存标签相关联的读取掩码，读取掩码标识先前访问的高速缓存行的段。

公开(公告)号：US11531472B2

公开(公告)日：2022-12-20

申请号：US17242037

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06F11/00 ,  G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F13/38 ,  G06F11/07 ,  G11C29/52 ,  H04L1/18 ,  H04L47/12 ,  H04L47/25 ,  H04L47/52

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.

公开(公告)号：US20210287027A1

公开(公告)日：2021-09-16

申请号：US17332369

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06K9/00

Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

公开(公告)号：US11023758B2

公开(公告)日：2021-06-01

申请号：US16249682

申请日：2019-01-16

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06K9/00

Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

公开(公告)号：US20210141541A1

公开(公告)日：2021-05-13

申请号：US17152465

申请日：2021-01-19

Applicant: Micron Technology, Inc.

Inventor： J. Thomas Pawlowski

IPC: G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F13/38 ,  G06F11/07 ,  G11C29/52 ,  H04L1/18 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873

Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.