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公开(公告)号：US20210055981A1
公开(公告)日：2021-02-25
申请号：US16545721
申请日：2019-08-20
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Kevin G. Werhane , Yoshinori Fujiwara , Christopher G. Wieduwilt , Jason M. Johnson , Minoru Someya
Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.
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公开(公告)号：US11675589B2
公开(公告)日：2023-06-13
申请号：US17464650
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Kevin G. Werhane , Daniel S. Miller
CPC classification number: G06F9/30116 , G06F13/4282
Abstract: Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.
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公开(公告)号：US11645134B2
公开(公告)日：2023-05-09
申请号：US16545721
申请日：2019-08-20
Applicant: Micron Technology, Inc.
Inventor： Daniel S. Miller , Kevin G. Werhane , Yoshinori Fujiwara , Christopher G. Wieduwilt , Jason M. Johnson , Minoru Someya
CPC classification number: G06F11/0751 , G06F11/0727 , G11C17/16 , H03K19/21
Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.
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公开(公告)号：US20220156148A1
公开(公告)日：2022-05-19
申请号：US17591362
申请日：2022-02-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Vivek Kotti , Christopher G. Wieduwilt , Jason M. Johnson , Kevin G. Werhane
IPC: G06F11/10 , G11C11/408
Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
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公开(公告)号：US11263078B2
公开(公告)日：2022-03-01
申请号：US16748554
申请日：2020-01-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Vivek Kotti , Christopher G. Wieduwilt , Jason M. Johnson , Kevin G. Werhane
IPC: G06F11/00 , G06F11/10 , G11C11/408 , G11C11/4096
Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
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Patent Agency Ranking
公开(公告)号：US11183260B1
公开(公告)日：2021-11-23
申请号：US17098865
申请日：2020-11-16
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Dave Jefferson , Jason M. Johnson , Vivek Kotti , Minoru Someya , Toru Ishikawa , Kevin G. Werhane
Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.
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公开(公告)号：US11054468B2
公开(公告)日：2021-07-06
申请号：US15993364
申请日：2018-05-30
Applicant: Micron Technology, Inc.
Inventor： Kevin G. Werhane , Nathaniel J. Meier
IPC: G01R31/317 , H01L21/00 , G09G1/00
Abstract: Methods, systems, and devices for testing a die using a segmented digital die ring are described. A segmented digital die ring may include multiple signal line segments, each coupled with a test segment circuit, and a control circuit. A test segment circuit may generate a digital feedback signal that indicates a condition of a respective signal line segment. The control circuit may generate a single output signal, indicative of the condition of the signal line segments. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die ring be minimized and a power consumption associated with the testing operation may be reduced.
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公开(公告)号：US20210200629A1
公开(公告)日：2021-07-01
申请号：US16748554
申请日：2020-01-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Vivek Kotti , Christopher G. Wieduwilt , Jason M. Johnson , Kevin G. Werhane
IPC: G06F11/10 , G11C11/408
Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity hits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
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公开(公告)号：US12100476B2
公开(公告)日：2024-09-24
申请号：US17942944
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Kari Crane , Kevin G. Werhane , Yoshinori Fujiwara , Jason M. Johnson , Takuya Tamano , Daniel S. Miller
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1063 , G11C17/16
Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
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公开(公告)号：US12100467B2
公开(公告)日：2024-09-24
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/027 , G11C29/24 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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