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    SENSE OPERATION FLAGS IN A MEMORY DEVICE
    11.
    发明申请
    SENSE OPERATION FLAGS IN A MEMORY DEVICE 有权
    在存储器中识别操作标志

    公开(公告)号：US20150363313A1

    公开(公告)日：2015-12-17

    申请号：US14833175

    申请日：2015-08-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F12/08 ,  G06F13/28 ,  G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

    Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

    3-D Memory Arrays
    16.
    发明申请
    3-D Memory Arrays 有权
    3-D内存数组

    公开(公告)号：US20140217488A1

    公开(公告)日：2014-08-07

    申请号：US13759627

    申请日：2013-02-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Deepak Thimmegowda ,  Brian Cleereman ,  Khaled Hasnat

    IPC: H01L29/78

    CPC classification number: H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

    Abstract translation: 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，这些栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。

    3-D memory arrays
    20.
    发明授权
    3-D memory arrays 有权
    3-D存储器阵列

    公开(公告)号：US09219070B2

    公开(公告)日：2015-12-22

    申请号：US13759627

    申请日：2013-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Deepak Thimmegowda ,  Brian Cleereman ,  Khaled Hasnat

    IPC: H01L29/41 ,  H01L29/417 ,  H01L27/115 ,  H01L27/02 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

    Abstract translation: 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，该栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。

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