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    Concurrent slow-fast memory cell programming
    11.
    发明授权
    Concurrent slow-fast memory cell programming 有权

    公开(公告)号：US12211552B2

    公开(公告)日：2025-01-28

    申请号：US18121846

    申请日：2023-03-15

    Applicant: Micron Technology, Inc.

    Inventor： Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Sheyang Ning ,  Jeffrey S. McNeil

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

    Abstract: Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.

    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
    15.
    发明申请
    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS 有权

    公开(公告)号：US20230039026A1

    公开(公告)日：2023-02-09

    申请号：US17396825

    申请日：2021-08-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

    FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS
    16.
    发明申请
    FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS 有权

    公开(公告)号：US20230034752A1

    公开(公告)日：2023-02-02

    申请号：US17833466

    申请日：2022-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

    Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.

    ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM
    18.
    发明申请
    ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220310165A1

    公开(公告)日：2022-09-29

    申请号：US17669074

    申请日：2022-02-10

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04

    Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and applies, during a first time period of the program operation, a ramping wordline voltage to a set of wordlines associated with the memory array. The control logic causes, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a programming level of a set of programming levels. The control logic further causes, during a second time period of the program operation, a set of programming pulses to be applied to the set of memory cells, wherein each programming pulse of the set of programming pulses programs each programming level of the set of programming levels associated with the identified set of memory cells.

    Memory device including dynamic programming voltage
    19.
    发明授权
    Memory device including dynamic programming voltage 有权

    公开(公告)号：US11335418B2

    公开(公告)日：2022-05-17

    申请号：US17135321

    申请日：2020-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Lawrence Celso Miranda

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

    Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

    Level shifting in all levels programming of a memory device in a memory sub-system
    20.
    发明授权
    Level shifting in all levels programming of a memory device in a memory sub-system 有权

    公开(公告)号：US12260914B2

    公开(公告)日：2025-03-25

    申请号：US17675447

    申请日：2022-02-18

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

    Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.

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