公开(公告)号：US12112819B2

公开(公告)日：2024-10-08

申请号：US18376198

申请日：2023-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12005 ,  G11C29/4401

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

公开(公告)号：US11798647B2

公开(公告)日：2023-10-24

申请号：US17681976

申请日：2022-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12005 ,  G11C29/4401

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

公开(公告)号：US20230170033A1

公开(公告)日：2023-06-01

申请号：US17987780

申请日：2022-11-15

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Luyen Vu ,  Lawrence Celso Miranda ,  Jeffrey Ming-Hung Tsai

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/26 ,  G11C16/102

Abstract: Control logic in a memory device initiates a first loop of a program operation, the first loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells of the plurality of memory cells associated with a first sub-set of the plurality of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level of the respective ones of the plurality of programming levels. The control logic further causes a first program verify voltage to be applied to the selected wordline during the program verify phase, and performs concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the first loop of the program operation.

公开(公告)号：US20180366203A1

公开(公告)日：2018-12-20

申请号：US16111319

申请日：2018-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/24 ,  G11C16/04 ,  G11C7/04 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/145 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US10127988B2

公开(公告)日：2018-11-13

申请号：US15248692

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/14

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US20180061497A1

公开(公告)日：2018-03-01

申请号：US15248692

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C5/145 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US20150228659A1

公开(公告)日：2015-08-13

申请号：US14175901

申请日：2014-02-07

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Mark A. Helm

IPC: H01L27/115 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

Abstract translation: 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最紧密的包装布置包括具有7个不同支柱的至少部分的重复支柱图案。 重复柱图案中的相应一个中的每个不同的支柱能够电耦合到多条数据线的不同数据线。 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最接近的包装布置包括具有7个不同柱的至少一部分的重复柱图形。 重复柱状图案的所有7个不同的柱由单个排水侧选择栅（SGD）包围。