公开(公告)号：US11626145B2

公开(公告)日：2023-04-11

申请号：US17360922

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H04L25/03 ,  H04B3/32 ,  G11C7/10

Abstract: Embodiments of the disclosure include signal processing methods to reduce crosstalk between signal lines of a channel bus using feed forward equalizers (FFEs) configured smear pulse response energy transmitted on signal lines of the channel to reduce pulse edge rates. The coefficients for the FFE may be based on crosstalk interference characteristics. Smearing or spreading pulse response energy across a longer time period using a FFE increases inter-symbol interference (ISI). To counter increased inter-symbol interference caused by smearing pulse response energy, receivers configured to recover symbol data transmitted on the channel bus may each include respective decision-feedback equalizers (DFEs) that are configured to filter ISI from transmitted symbols based on previous symbol decisions of the channel. The combination of the FFE configured to smear pulse responses and the DFE to filter ISI may improve data eye quality for recovery of transmitted data on a channel bus when crosstalk dominates noise.

公开(公告)号：US20220342814A1

公开(公告)日：2022-10-27

申请号：US17861627

申请日：2022-07-11

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11386004B2

公开(公告)日：2022-07-12

申请号：US16797618

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G11C16/04 ,  G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

Abstract: Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US20220004317A1

公开(公告)日：2022-01-06

申请号：US17360943

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US20210383849A1

公开(公告)日：2021-12-09

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11948661B2

公开(公告)日：2024-04-02

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11942404B2

公开(公告)日：2024-03-26

申请号：US17411879

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Scott R. Cyr ,  Stephen F. Moxham ,  Matthew A. Prather ,  Scott Smith

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16235 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14361

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

公开(公告)号：US20240070069A1

公开(公告)日：2024-02-29

申请号：US18215474

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US20240063188A1

公开(公告)日：2024-02-22

申请号：US18499087

申请日：2023-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

公开(公告)号：US11514961B2

公开(公告)日：2022-11-29

申请号：US17466961

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie

IPC: G11C5/06 ,  G11C8/18 ,  G06F15/173 ,  G11C7/10 ,  G11C8/06

Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.