公开(公告)号：US11776625B2

公开(公告)日：2023-10-03

申请号：US17496667

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Hari Giduturi

IPC: G11C13/00 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C13/0038 ,  G11C5/145 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

公开(公告)号：US11587614B2

公开(公告)日：2023-02-21

申请号：US17394778

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Josephine Tiu Hamada ,  Kenneth Richard Surdyk ,  Lingming Yang ,  Mingdong Cui

IPC: G11C11/16 ,  G11C11/56 ,  G11C11/4074

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

公开(公告)号：US11380394B2

公开(公告)日：2022-07-05

申请号：US17158984

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Michel Ibrahim Ishac

IPC: G11C11/419 ,  G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.

公开(公告)号：US20220093190A1

公开(公告)日：2022-03-24

申请号：US17487792

申请日：2021-09-28

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

公开(公告)号：US11114156B2

公开(公告)日：2021-09-07

申请号：US16660569

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Josephine Tiu Hamada ,  Kenneth Richard Surdyk ,  Lingming Yang ,  Mingdong Cui

IPC: G11C11/16 ,  G11C11/56 ,  G11C11/4074

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

公开(公告)号：US20210118497A1

公开(公告)日：2021-04-22

申请号：US16660569

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Josephine Tiu Hamada ,  Kenneth Richard Surdyk ,  Lingming Yang ,  Mingdong Cui

IPC: G11C11/56 ,  G11C11/4074

Abstract: An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

公开(公告)号：US10396795B1

公开(公告)日：2019-08-27

申请号：US15926548

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hari Giduturi

IPC: H03K19/0185 ,  H03K17/10 ,  H03K5/003 ,  H03K5/00

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

公开(公告)号：US20190080756A1

公开(公告)日：2019-03-14

申请号：US16190563

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C13/00 ,  G11C29/50

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. All example apparatus, may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US20180090204A1

公开(公告)日：2018-03-29

申请号：US15828402

申请日：2017-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C13/00 ,  G11C29/50

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US09627052B1

公开(公告)日：2017-04-18

申请号：US14950413

申请日：2015-11-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.