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公开(公告)号：US11693587B2
公开(公告)日：2023-07-04
申请号：US17404875
申请日：2021-08-17
Applicant: Micron Technology, Inc.
Inventor： Sandeep Reddy Kadasani , Scott Anthony Stoller , Pitamber Shukla , Niccolo' Righetti , Chi Ming Chu
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A read operation is performed on a memory device in accordance with a pass-through voltage setting that defines a pass-through voltage applied to one or more cells of the memory device during read operations. A number of zero bits read from the memory device based on the read operation are counted and compared with a threshold value. Based on the number of zero bits exceeding the threshold value, the pass-through voltage is increased by adjusting the pass-through voltage setting.
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公开(公告)号：US20220391125A1
公开(公告)日：2022-12-08
申请号：US17890885
申请日：2022-08-18
Applicant: Micron Technology, Inc.
Inventor： Priya Venkataraman , Pitamber Shukla , Scott A. Stoller , Giuseppina Puzzilli , Niccolo' Righetti
IPC: G06F3/06
Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.
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公开(公告)号：US20220291865A1
公开(公告)日：2022-09-15
申请号：US17829861
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.
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公开(公告)号：US20220215895A1
公开(公告)日：2022-07-07
申请号：US17700085
申请日：2022-03-21
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.
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公开(公告)号：US20220068412A1
公开(公告)日：2022-03-03
申请号：US17453289
申请日：2021-11-02
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, JR. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
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Patent Agency Ranking
公开(公告)号：US20220057944A1
公开(公告)日：2022-02-24
申请号：US17001121
申请日：2020-08-24
Applicant: Micron Technology, Inc.
Inventor： Jeremy Binfet , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Kishore K. Muchherla , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device is further coupled to the processing device and to a primary power supply and a secondary power supply. The processing device is to determine, based at least in part on availability of the primary power supply to the memory device, whether to operate the memory device with a first trim tailored to data reliability or a second trim tailored to programming time. The processing device is further to operate the memory device with the determined one of the first trim or the second trim.
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公开(公告)号：US12002516B2
公开(公告)日：2024-06-04
申请号：US17831350
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Inventor： Zhongyuan Lu , Niccolo' Righetti
Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.
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18.发明授权公开(公告)号：US11972114B2
公开(公告)日：2024-04-30
申请号：US17867204
申请日：2022-07-18
Applicant: Micron Technology, Inc.
Inventor： Sandeep Reddy Kadasani , Pitamber Shukla , Scott Anthony Stoller , Niccolo' Righetti
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0688
Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.
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公开(公告)号：US20240071522A1
公开(公告)日：2024-02-29
申请号：US17895886
申请日：2022-08-25
Applicant: Micron Technology, Inc.
Inventor： Nicola Ciocchini , Animesh R. Chowdhury , Kishore Kumar Muchherla , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Jonathan S. Parry
CPC classification number: G11C16/3427 , G11C16/08 , G11C16/26
Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.
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公开(公告)号：US20240070023A1
公开(公告)日：2024-02-29
申请号：US17897869
申请日：2022-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Niccolo' Righetti , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , James Fitzpatrick , Ugo Russo
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/1435
Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
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