公开(公告)号：US11244954B2

公开(公告)日：2022-02-08

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20210358759A1

公开(公告)日：2021-11-18

申请号：US17391345

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Eric Freeman ,  Paolo Tessariol

IPC: H01L21/311 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

公开(公告)号：US11177271B2

公开(公告)日：2021-11-16

申请号：US15705179

申请日：2017-09-14

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11565

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US20210225938A1

公开(公告)日：2021-07-22

申请号：US16771658

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Paolo Tessariol

IPC: H01L27/24 ,  G11C8/08

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

公开(公告)号：US20210201993A1

公开(公告)日：2021-07-01

申请号：US17011018

申请日：2020-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

公开(公告)号：US20200168622A1

公开(公告)日：2020-05-28

申请号：US16200158

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  M. Jared Barclay ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28

Abstract: A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.

公开(公告)号：US10366901B2

公开(公告)日：2019-07-30

申请号：US15451090

申请日：2017-03-06

Applicant: Micron Technology, Inc.

Inventor： Eric Freeman ,  Paolo Tessariol

IPC: H01L21/311 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

公开(公告)号：US10290581B2

公开(公告)日：2019-05-14

申请号：US15916575

申请日：2018-03-09

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11517 ,  H01L27/11548

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20180254283A1

公开(公告)日：2018-09-06

申请号：US15451090

申请日：2017-03-06

Applicant: Micron Technology, Inc.

Inventor： Eric Freeman ,  Paolo Tessariol

IPC: H01L27/11529 ,  H01L49/02 ,  H01L27/11573 ,  H01L21/311 ,  H01L27/11531

CPC classification number: H01L21/31111 ,  H01L23/5223 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

公开(公告)号：US20160104716A1

公开(公告)日：2016-04-14

申请号：US14969709

申请日：2015-12-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto M. Meotto ,  Giulio Albini ,  Paolo Tessariol ,  Paola Bacciaglia ,  Marcello Mariani

IPC: H01L27/115 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/02233 ,  H01L21/28282 ,  H01L21/76224 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/66833 ,  H01L29/792

Abstract: Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.

Abstract translation: 在半导体衬底的第一区域上形成包含存储单元的集成电路器件和在半导体衬底的从第一区域凹入的第二区域上的栅极结构的方法。 所述方法包括形成对存储单元和栅极结构都是共同的金属。