公开(公告)号：US20140284812A1

公开(公告)日：2014-09-25

申请号：US14302160

申请日：2014-06-11

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成，随后可以与第一组横向的第二组平行条纹掩模形成。 例如，可以使用一组掩模来蚀刻介电层，以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后，该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。

公开(公告)号：US11600665B2

公开(公告)日：2023-03-07

申请号：US17069347

申请日：2020-10-13

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L45/00 ,  H01L27/24

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US10157788B2

公开(公告)日：2018-12-18

申请号：US15000935

申请日：2016-01-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

IPC: H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

公开(公告)号：US10084016B2

公开(公告)日：2018-09-25

申请号：US14086460

申请日：2013-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

公开(公告)号：US20180151415A1

公开(公告)日：2018-05-31

申请号：US15881539

申请日：2018-01-26

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US09899254B2

公开(公告)日：2018-02-20

申请号：US15471420

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US20160104748A1

公开(公告)日：2016-04-14

申请号：US14970602

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini ,  Gabriel L. Donadio

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  G11C5/063 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

公开(公告)号：US09172037B2

公开(公告)日：2015-10-27

申请号：US14252145

申请日：2014-04-14

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Fabio Pellizzer ,  Carmela Cupeta ,  Nicola Nastasi

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/14 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry.

Abstract translation: 提供了存储器阵列及其形成方法。 形成存储器阵列的一个示例性方法可以包括在多个通孔中以及在衬底结构上形成导电材料，所述导电材料用作阵列的多个导电线并将导线的数量耦合到阵列电路 。

公开(公告)号：US10367033B2

公开(公告)日：2019-07-30

申请号：US16112570

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

公开(公告)号：US20170200635A1

公开(公告)日：2017-07-13

申请号：US15471420

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.