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    APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION
    11.
    发明公开
    APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION 审中-公开

    公开(公告)号：US20240071549A1

    公开(公告)日：2024-02-29

    申请号：US17822909

    申请日：2022-08-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi

    IPC: G11C29/42 ,  G11C7/10 ,  G11C29/32

    CPC classification number: G11C29/42 ,  G11C7/1069 ,  G11C29/32

    Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

    APPARATUSES, SYSTEMS, AND METHODS FOR FORCED ERROR CHECK AND SCRUB READOUTS
    12.
    发明公开
    APPARATUSES, SYSTEMS, AND METHODS FOR FORCED ERROR CHECK AND SCRUB READOUTS 审中-公开

    公开(公告)号：US20230185665A1

    公开(公告)日：2023-06-15

    申请号：US18167768

    申请日：2023-02-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi

    IPC: G06F11/10 ,  G11C11/406

    CPC classification number: G06F11/1068 ,  G11C11/40615 ,  G11C11/4063

    Abstract: Apparatuses, systems, and methods for forced error check and scrub (ECS) readouts. A memory may perform a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit may count errors which are detected, and set a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

    Routing Assignments Based on Error Correction Capabilities
    13.
    发明申请
    Routing Assignments Based on Error Correction Capabilities 有权

    公开(公告)号：US20230121163A1

    公开(公告)日：2023-04-20

    申请号：US17505122

    申请日：2021-10-19

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Smith ,  Randy Brian Drake ,  Brian Ladner ,  Thanh Kim Mai ,  Sujeet Ayyapureddi ,  Matthew Alan Prather

    IPC: G06F13/40 ,  G06F13/16 ,  G06F11/10

    Abstract: The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

    Apparatuses and methods for sketch circuits for refresh binning
    15.
    发明授权
    Apparatuses and methods for sketch circuits for refresh binning 有权

    公开(公告)号：US11600314B2

    公开(公告)日：2023-03-07

    申请号：US17201941

    申请日：2021-03-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

    IPC: G11C11/406 ,  G11C11/408 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

    Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).

    Apparatuses, systems, and methods for probabilistic data structures for error tracking
    16.
    发明授权
    Apparatuses, systems, and methods for probabilistic data structures for error tracking 有权

    公开(公告)号：US11342041B2

    公开(公告)日：2022-05-24

    申请号：US17003486

    申请日：2020-08-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi

    IPC: G11C29/18 ,  G11C29/44 ,  G11C29/42 ,  G11C29/12

    Abstract: Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.

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