公开(公告)号：US10546862B1

公开(公告)日：2020-01-28

申请号：US16248584

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Suraj J. Mathew

IPC: H01L27/108 ,  H01L21/768

Abstract: Some embodiments include an integrated assembly having active-region-pillars extending upwardly from a base. Each of the active-region-pillars has a pair of storage-element-contact-regions, and a digit-line-contact-region between the storage-element-contact-regions. The integrated assembly includes, along a cross-section, a first digit-line-contact-region adjacent a first storage-element-contact-region. The first digit-line-contact-region is recessed relative to the first storage-element-contact-region. A first digit-line is coupled with the first digit-line-contact-region. A second digit-line is laterally offset from the first digit-line. An insulative material is between the first digit-line and the first storage-element-contact-region. A cup-shaped indentation extends into the insulative material and the first storage-element-contact-region. Insulative spacers are along sidewalls of the first and second digit-lines, and include first material. First and second insulative pillars are over the first and second digit-lines, and include second material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10319724B2

公开(公告)日：2019-06-11

申请号：US16033377

申请日：2018-07-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L29/94 ,  H01L23/528 ,  H01L29/08

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US08722480B2

公开(公告)日：2014-05-13

申请号：US13751537

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： F. Daniel Gealy ,  Suraj J. Mathew ,  Cancheepuram V. Srividya

IPC: H01L27/11 ,  H01L27/092

CPC classification number: H01L21/28079 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract translation: 提供了包括第一和第二源极/漏极区域的晶体管，沟道区域和栅极堆叠，其在衬底上具有第一栅极电介质，第一栅极电介质的介电常数高于二氧化硅的介电常数，以及金属材料 与第一栅极电介质接触，金属材料被掺杂惰性元素。 还提供了包括晶体管的集成电路和形成晶体管的方法。

公开(公告)号：US20130237023A1

公开(公告)日：2013-09-12

申请号：US13869112

申请日：2013-04-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US20190326292A1

公开(公告)日：2019-10-24

申请号：US16459956

申请日：2019-07-02

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/405 ,  G11C5/06

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180301454A1

公开(公告)日：2018-10-18

申请号：US16006301

申请日：2018-06-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum SImsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US10079235B2

公开(公告)日：2018-09-18

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180061836A1

公开(公告)日：2018-03-01

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20150249089A1

公开(公告)日：2015-09-03

申请号：US14712291

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/02

CPC classification number: H01L27/10832 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/28525 ,  H01L27/10861 ,  H01L27/10873 ,  H01L29/945

Abstract: A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

Abstract translation: 存储单元包括晶体管器件，其包括一对源极/漏极，包括沟道的主体以及可操作地邻近沟道的栅极结构。 存储单元包括电容器，该电容器包括一对在其间具有电容器电介质的电容器电极。 电容器电极之一是通道或电耦合到通道。 电容器电极中的另一个包括主体而不是通道的一部分。 还公开了方法。

公开(公告)号：US09054216B2

公开(公告)日：2015-06-09

申请号：US14319201

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66 ,  H01L29/417 ,  H01L27/11

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。