公开(公告)号：US20240356554A1

公开(公告)日：2024-10-24

申请号：US18542585

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: H03K19/0185 ,  H10B12/00

CPC classification number: H03K19/018521 ,  H10B12/50

Abstract: A memory device includes a level shifting circuitry. The level shifting circuitry includes an input circuitry configured to receive an input to the level shifting circuitry in a first voltage domain. The level shifting circuitry also includes a cross-junction circuitry electrically coupled to a first node of the input circuitry comprising multiple transistors that are electrically coupled in a cross-junction. The level shifting circuitry also includes an output staging circuitry electrically coupled to a second node of the cross-junction circuitry. The output staging circuitry is configured to transmit an output in a second voltage domain. The output staging circuitry includes a transistor and voltage stress reduction circuitry configured to mitigate degradation of the transistor by reducing voltage stresses across the transistor during transitions in the level shifting circuitry.

公开(公告)号：US11804260B2

公开(公告)日：2023-10-31

申请号：US17746542

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4096 ,  H03K19/173 ,  G11C5/06 ,  G11C11/404

CPC classification number: G11C11/4091 ,  G11C5/06 ,  G11C11/4045 ,  G11C11/4096 ,  H03K19/1737

Abstract: A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

公开(公告)号：US11699473B2

公开(公告)日：2023-07-11

申请号：US17111311

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Tae H. Kim

IPC: G11C8/08 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

公开(公告)号：US11417391B2

公开(公告)日：2022-08-16

申请号：US17006097

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C11/4093 ,  H03K19/0185 ,  H03K3/356

Abstract: A memory device includes a level down shifting driver circuit. The level down shifting driver circuit include input circuitry having at least one input port, and a cross-junction circuitry electrically coupled to the input circuitry and configured to receive a first signal from the input circuitry to drive one or more devices included in the cross-junction circuitry. The level down shifting driver circuit further includes an output drive circuitry electrically coupled to the cross-junction circuitry and configured to receive a second signal from the cross-junction circuitry, wherein the output drive circuitry comprises an output line configured to deliver a first voltage output based on a first input voltage received by the input circuitry, and a second voltage output based on a second input voltage received by the input circuitry.

公开(公告)号：US20210327490A1

公开(公告)日：2021-10-21

申请号：US16853417

申请日：2020-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sang-Kyun Park ,  Tae H. Kim

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C5/06

Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.

公开(公告)号：US10998027B2

公开(公告)日：2021-05-04

申请号：US16035147

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/22 ,  H01L27/1159 ,  H01L27/11592 ,  G11C5/02

Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.

公开(公告)号：US20210057009A1

公开(公告)日：2021-02-25

申请号：US16548242

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C8/08 ,  G11C11/408 ,  G11C8/14

Abstract: A word line driver circuit is disclosed. A word line driver circuit may include a circuit configured to generate a clamped voltage based on a first fixed supply voltage and in response to receipt of a first control signal triggering an active mode. The circuitry may further be configured to generate an internal global word line voltage based on the clamped voltage during the active mode. Further, the word line driver circuit may include at least one main word line driver configured to receive the internal global word line voltage and generate a global word line voltage. Additionally, the word line driver circuit may include at least one sub word line driver configured to receive the global word line voltage and generate a word line voltage.

公开(公告)号：US10854268B2

公开(公告)日：2020-12-01

申请号：US16536141

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

公开(公告)号：US20190392872A1

公开(公告)日：2019-12-26

申请号：US16017826

申请日：2018-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4074 ,  G11C7/12 ,  G11C8/10

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit hue, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.

公开(公告)号：US20190259434A1

公开(公告)日：2019-08-22

申请号：US16405075

申请日：2019-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim

IPC: G11C8/10 ,  G11C8/08 ,  G11C8/14

Abstract: Methods and apparatuses of providing word line voltages are disclosed. An example method includes: activating and deactivating a word line. Activating the word line includes: rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and supplying the first node with an active voltage. Deactivating the word line includes: changing a voltage of the first node from the active voltage to an inactive voltage; changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage; rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and rendering the first and second transistors non-conductive and conductive, respectively, after the third transistor has been rendered conductive.