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    Parity protection
    11.
    发明授权
    Parity protection 有权

    公开(公告)号：US11106530B2

    公开(公告)日：2021-08-31

    申请号：US16723836

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

    IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

    Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

    VARIABLE READ ERROR CODE CORRECTION
    12.
    发明申请
    VARIABLE READ ERROR CODE CORRECTION 有权

    公开(公告)号：US20210175902A1

    公开(公告)日：2021-06-10

    申请号：US17181712

    申请日：2021-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Ting Luo

    IPC: H03M13/11 ,  G06F11/10

    Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.

    SECURE ERASE FOR DATA CORRUPTION
    13.
    发明申请
    SECURE ERASE FOR DATA CORRUPTION 有权

    公开(公告)号：US20210151111A1

    公开(公告)日：2021-05-20

    申请号：US17158555

    申请日：2021-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34

    Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

    Managing partial superblocks in a NAND device
    14.
    发明授权
    Managing partial superblocks in a NAND device 有权

    公开(公告)号：US10996867B2

    公开(公告)日：2021-05-04

    申请号：US16506372

    申请日：2019-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Ting Luo

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027

    Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

    Memory pattern management for improved data retention in memory devices
    19.
    发明授权
    Memory pattern management for improved data retention in memory devices 有权

    公开(公告)号：US12242734B2

    公开(公告)日：2025-03-04

    申请号：US18237668

    申请日：2023-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Guang Hu ,  Ting Luo

    IPC: G06F3/06

    Abstract: A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.

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