公开(公告)号：US12094534B2

公开(公告)日：2024-09-17

申请号：US18459461

申请日：2023-09-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng

IPC: G11C15/04 ,  G11C7/14

CPC classification number: G11C15/046 ,  G11C7/14

Abstract: The application provides a content addressable memory (CAM) memory device, a CAM cell and a method for searching and comparing data thereof. The CAM device includes: a plurality of CAM cells; and an electrical characteristic detection circuit coupled to the CAM cells; wherein in data searching, a search data is compared with a storage data stored in the CAM cells, the CAM cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

公开(公告)号：US12069857B2

公开(公告)日：2024-08-20

申请号：US17408535

申请日：2021-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Feng-Min Lee ,  Po-Hao Tseng

IPC: H10B41/35 ,  H01L21/28 ,  H01L29/66

CPC classification number: H10B41/35 ,  H01L29/40114 ,  H01L29/66825

Abstract: The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

公开(公告)号：US11875850B2

公开(公告)日：2024-01-16

申请号：US17730259

申请日：2022-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory strings; and an electrical characteristic detection circuit. In data searching, a search data is compared with a storage data stored in the CAM memory strings, the CAM memory strings generate a plurality of memory string currents, the electrical characteristic detection circuit detects the memory string currents to generate a plurality of sensing results, or detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory string to generate the plurality of search results. The storage data and the search data is a range storage data and a single-bit search data, or the storage data and the search data is a single-bit storage data and a range search data.

公开(公告)号：US11790990B2

公开(公告)日：2023-10-17

申请号：US17717192

申请日：2022-04-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng

IPC: G11C15/04 ,  G11C7/14

CPC classification number: G11C15/046 ,  G11C7/14

Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

公开(公告)号：US20230253032A1

公开(公告)日：2023-08-10

申请号：US18303194

申请日：2023-04-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G06F7/523 ,  G11C11/408 ,  G06F7/501 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4091 ,  G06F7/523 ,  G11C11/4085 ,  G06F7/501 ,  G11C11/4094

Abstract: An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

公开(公告)号：US11664070B2

公开(公告)日：2023-05-30

申请号：US17344555

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F7/523 ,  G06F7/501

CPC classification number: G11C11/4093 ,  G06F7/501 ,  G06F7/523 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

公开(公告)号：US20230095392A1

公开(公告)日：2023-03-30

申请号：US18073366

申请日：2022-12-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  G11C11/56 ,  H01L27/1157

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US09811689B1

公开(公告)日：2017-11-07

申请号：US15391062

申请日：2016-12-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Kai-Chieh Hsu ,  Feng-Min Lee ,  Yu-Yu Lin

IPC: G11C13/00 ,  G06F3/06 ,  H01L45/00 ,  G06F21/73 ,  H04L9/08 ,  H01L27/24 ,  G11C11/417 ,  G06F21/70 ,  H04L9/32

CPC classification number: G06F21/73 ,  G06F21/70 ,  G11C11/417 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0088 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H04L9/0866 ,  H04L9/3278

Abstract: A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.

公开(公告)号：US12211550B2

公开(公告)日：2025-01-28

申请号：US18420874

申请日：2024-01-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/04 ,  G11C15/04 ,  G11C16/04 ,  G11C11/404

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

公开(公告)号：US12190941B2

公开(公告)日：2025-01-07

申请号：US18147015

申请日：2022-12-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee

IPC: G11C11/4091

Abstract: A memory cell and a memory device are provided. The memory cell comprises: a write transistor; and a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data; wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable.