公开(公告)号：US11257547B2

公开(公告)日：2022-02-22

申请号：US17105669

申请日：2020-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Hsuan Hsu ,  Po-Kai Hsu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/14 ,  G06N3/04 ,  G11C11/56

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

公开(公告)号：US11894065B2

公开(公告)日：2024-02-06

申请号：US17569424

申请日：2022-01-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

公开(公告)号：US20240028211A1

公开(公告)日：2024-01-25

申请号：US18161900

申请日：2023-01-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Teng-Hao Yeh ,  Chih-Chang Hsieh ,  Chun-Hsiung Hung ,  Yung-Chun LI

IPC: G06F3/06 ,  G11C16/28

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/28

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

公开(公告)号：US20180102177A1

公开(公告)日：2018-04-12

申请号：US15290376

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chen-Jun WU ,  Chih-Chang Hsieh ,  Tzu-Hsuan Hsu ,  Hang-Ting LUE

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C2211/562 ,  G11C2211/5648

Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i−1).

公开(公告)号：US09263143B2

公开(公告)日：2016-02-16

申请号：US14330106

申请日：2014-07-14

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Chen-Jun Wu

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/16 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.

Abstract translation: 一种三维（3D）存储器件的数据擦除方法，包括以下步骤。 首先，在擦除操作的第一阶段中，将第一电压施加到半导体通道的第一半导体通道，以擦除存储在第一半导体通道上限定的存储单元中的数据，并将第二电压施加到第二半导体通道 的半导体通道，其中第二半导体沟道与第一半导体沟道相邻。 然后，在擦除操作的第二阶段中，将第二电压施加到第一半导体沟道，并将第一电压施加到第二半导体沟道。