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    Multiple phase change materials in an integrated circuit for system on a chip application
    11.
    发明授权
    Multiple phase change materials in an integrated circuit for system on a chip application 有权
    用于芯片应用系统的集成电路中的多相变材料

    公开(公告)号：US09336879B2

    公开(公告)日：2016-05-10

    申请号：US14603647

    申请日：2015-01-23

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hsiang-Lan Lung ,  Chao-I Wu ,  Wei-Chih Chien

    IPC: H01L21/8242 ,  G11C13/00 ,  H01L45/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  H01L45/06 ,  H01L45/144

    Abstract: A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.

    Abstract translation: 一种装置包括具有存储元件的第一和第二多个存储单元，以及在第一和第二多个存储单元上的第一和第二封盖材料。 第一和第二封盖材料可以包括较低和较高密度的氮化硅。 存储器元件可以包括可编程电阻存储器材料，并且封盖材料可以接触存储器元件。 第一和第二多个存储器单元可以具有公共的单元结构。 罐中的第一存储器单元可以包括顶部和底部电极，其间具有记忆材料，并且第一封盖材料与记忆材料接触。 控制电路可以对第一和第二多个存储单元应用不同的写入算法。 通过使用不同的封盖材料但是具有相同的单元结构形成第一和第二封盖层，第一和第二组存储器单元可以具有不同的操作存储器特性。

    Resistive memory and fabricating method thereof
    13.
    发明授权
    Resistive memory and fabricating method thereof 有权
    电阻记忆及其制造方法

    公开(公告)号：US09196828B2

    公开(公告)日：2015-11-24

    申请号：US13849422

    申请日：2013-03-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Ming-Hsiu Lee ,  Wei-Chih Chien

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

    Abstract: A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode.

    Abstract translation: 提供了一种电阻式存储器及其制造方法。 电阻存储器包括第一和第二电极，可变电阻材料层，第一介电层和第二电介质层。 第一电极包括第一部分和第二部分。 第二电极与第一电极相对设置。 可变电阻材料层包括侧壁和彼此相对的第一和第二表面，其中第一表面与第一电极的第一部分连接，第二表面与第二电极电连接。 第二部分围绕可变电阻材料层的侧壁并与第一部分连接。 第一电介质层设置在第一和第二电极之间。 第二电介质层设置在可变电阻材料层和第一电极的第二部分之间。

    Fast switching 3D cross-point array
    17.
    发明授权
    Fast switching 3D cross-point array 有权

    公开(公告)号：US10157671B1

    公开(公告)日：2018-12-18

    申请号：US15702208

    申请日：2017-09-12

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hsiang-Lan Lung ,  Wei-Chih Chien

    IPC: G11C11/00 ,  G11C13/00

    Abstract: An integrated circuit includes a memory array including a plurality of memory cells disposed at respective cross points of a plurality of first access lines and a plurality of second access lines. A selected memory cell has a first threshold voltage Vth(S) of set state and a second threshold voltage Vth(R) of reset state. Control circuitry is configured to apply a write voltage Vw to the selected first access line during a write operation, to apply a read voltage Vr to the selected first access line during a read operation, and to apply a same inhibit voltage Vu to unselected first and second access lines during the write and read operations, where ½Vw>Vu>Vw−Vth(S).

    MEMORY DEVICE AND OPERATION METHOD
    20.
    发明申请
    MEMORY DEVICE AND OPERATION METHOD 有权
    存储器和操作方法

    公开(公告)号：US20160328288A1

    公开(公告)日：2016-11-10

    申请号：US14703183

    申请日：2015-05-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hsin-Yi Ho ,  Hsiang-Lan Lung ,  Wei-Chih Chien ,  Tu-Shun Chen ,  Chia-Jung Chen

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0683 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

    Abstract translation: 提供了一种存储器件及其操作方法，并且存储器件的操作方法包括以下步骤。 执行编程操作以将原始数据写入存储器件中的第一存储器阵列。 验证第一存储器阵列中的原始数据，并根据验证结果确定是否生成写入信号。 根据原始数据生成纠错码，并将纠错码和写入地址临时存储在存储装置的缓冲电路中。 当产生写入信号时，将缓冲电路中的纠错码和写入地址写入存储器件中的第二存储器阵列。

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