公开(公告)号：US20130265819A1

公开(公告)日：2013-10-10

申请号：US13751763

申请日：2013-01-28

申请人： David Rennie ,  Manoj Sachdev

发明人： David Rennie ,  Manoj Sachdev

IPC分类号： G11C11/412

CPC分类号： G11C11/412 ,  G11C11/4125 ,  H03K19/007

摘要： A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

摘要翻译： 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的核心存储节点和互补的外部存储节点。 外部存储节点用于限制核心存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，核心存储节点用于限制具有相同效果的外部存储节点之间的反馈。 与其他强大的存储单元相比，该单元具有优点，因为在电源电压和地之间只有两条路径限制漏电功率。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US08363455B2

公开(公告)日：2013-01-29

申请号：US12630947

申请日：2009-12-04

申请人： David Rennie ,  Manoj Sachdev

发明人： David Rennie ,  Manoj Sachdev

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/4125 ,  H03K19/007

摘要： A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

摘要翻译： 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的核心存储节点和互补的外部存储节点。 外部存储节点用于限制核心存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，核心存储节点用于限制具有相同效果的外部存储节点之间的反馈。 与其他强大的存储单元相比，该单元具有优点，因为在电源电压和地之间只有两条路径限制漏电功率。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US08164943B2

公开(公告)日：2012-04-24

申请号：US12749857

申请日：2010-03-30

申请人： Manoj Sachdev ,  David Rennie

发明人： Manoj Sachdev ,  David Rennie

IPC分类号： G11C11/00

CPC分类号： G11C11/4125 ,  G11C11/413 ,  H03K3/356165 ,  H03K3/356182

摘要： A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the lower storage nodes act to limit feedback between the upper storage nodes with the same effect. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

摘要翻译： 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的下部存储节点和互补的上部存储节点。 上部存储节点用于限制下层存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，较低的存储节点用于限制具有相同效果的上层存储节点之间的反馈。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US20110298496A1

公开(公告)日：2011-12-08

申请号：US13151276

申请日：2011-06-02

申请人： David Rennie ,  Manoj Sachdev

发明人： David Rennie ,  Manoj Sachdev

IPC分类号： H03F3/45

CPC分类号： G11C7/065 ,  G11C11/413

摘要： A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.

摘要翻译： 提供了一种用于具有多个存储单元的存储器阵列中的读出放大器。 感测放大器提供低功耗，快速感测和高产量感测操作。 读出放大器的输入是SRAM列的差分位线，它们通过两个PMOS晶体管的源极耦合到读出放大器。 由两个NMOS晶体管和上述PMOS晶体管组成的CMOS锁存元件用于放大差分位线电压之间的任何差异，并将读出放大器的输出节点解析为全摆幅值。 闭锁元件门控有两个附加的PMOS晶体管，其用于阻止锁存操作，直到读出放大器被使能。 一个或多个均衡晶体管确保闩锁保持在亚稳态，直到其被使能。 一旦闩锁已经解决，除了泄漏外，它不会消耗直流电。

公开(公告)号：US20100246242A1

公开(公告)日：2010-09-30

申请号：US12749857

申请日：2010-03-30

申请人： Manoj Sachdev ,  David Rennie

发明人： Manoj Sachdev ,  David Rennie

IPC分类号： G11C11/00 ,  H03K19/173

CPC分类号： G11C11/4125 ,  G11C11/413 ,  H03K3/356165 ,  H03K3/356182

摘要： A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary lower storage nodes and complementary upper storage nodes. The upper storage nodes act to limit feedback between the lower storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the lower storage nodes act to limit feedback between the upper storage nodes with the same effect. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

摘要翻译： 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的下部存储节点和互补的上部存储节点。 上部存储节点用于限制下层存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，较低的存储节点用于限制具有相同效果的上层存储节点之间的反馈。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US20100195374A1

公开(公告)日：2010-08-05

申请号：US12630947

申请日：2009-12-04

申请人： David Rennie ,  Manoj Sachdev

发明人： David Rennie ,  Manoj Sachdev

IPC分类号： G11C11/00 ,  H03K19/173

CPC分类号： G11C11/412 ,  G11C11/4125 ,  H03K19/007

摘要： A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.

摘要翻译： 存储单元具有对软错误的改进的鲁棒性。 存储单元包括互补的核心存储节点和互补的外部存储节点。 外部存储节点用于限制核心存储节点之间的反馈，并且能够在发生软错误的情况下恢复核心存储节点的逻辑状态。 类似地，核心存储节点用于限制具有相同效果的外部存储节点之间的反馈。 与其他强大的存储单元相比，该单元具有优点，因为在电源电压和地之间只有两条路径限制漏电功率。 利用所提出的存储单元的SRAM单元可以通过配置成将互补存储节点选择性地耦合到相应位线的两个存取晶体管来实现。 可以使用选择性地将数据耦合到所提出的存储单元中的各种传输门来实现触发器。

公开(公告)号：US5831463A

公开(公告)日：1998-11-03

申请号：US696311

申请日：1996-08-13

申请人： Manoj Sachdev

发明人： Manoj Sachdev

IPC分类号： G01R31/30 ,  H03K3/037 ,  H03K19/173 ,  H03K3/3562

CPC分类号： G01R31/3008 ,  G01R31/3004 ,  H03K3/0372

摘要： A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.

摘要翻译： 主从触发器具有在输入和输出之间级联的主从锁存器。 每个锁存器都有两个逆变器直接连接到另一个头尾。 锁存器通过缓冲器和时钟控制的通过门耦合。 该架构减少了通过门和时钟线的数量，改善了保持时间，并提高了与已知触发器的IDDQ可测试性。

公开(公告)号：US5751141A

公开(公告)日：1998-05-12

申请号：US532338

申请日：1995-09-21

申请人： Manoj Sachdev ,  Botjo Atzema

发明人： Manoj Sachdev ,  Botjo Atzema

IPC分类号： G01R31/316 ,  G01R31/28 ,  G01R31/30 ,  G05F3/24 ,  H01L21/822 ,  H01L27/04 ,  H03M1/10 ,  H03M1/36 ,  G05F3/04 ,  H01H31/02

CPC分类号： H03M1/108 ,  G01R31/3004 ,  G01R31/3008 ,  H03M1/36

摘要： A bias generator is tested in an I.sub.DDQ -scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.

摘要翻译： 通过将各自的偏置电压施加到由相应的NFET分别门控的相应PFET，以IDDQ方案测试偏置发生器。 这允许测量静态电流。 偏置电压的任何偏差被转换为静态电流的偏差。

公开(公告)号：US07714628B2

公开(公告)日：2010-05-11

申请号：US12059238

申请日：2008-03-31

申请人： Manoj Sachdev ,  Shah M. Jahinuzzaman

发明人： Manoj Sachdev ,  Shah M. Jahinuzzaman

IPC分类号： H03K3/356

CPC分类号： G11C7/02 ,  G11C11/4125

摘要： A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled to the storage unit. The transfer unit includes a plurality of input nodes adapted to receive said at least one data signal and said at least one clock signal; a first output node for providing a sampled data signal in response to said at least one clock signal and said at least one data signal; and a second output node for providing a sampled inverse data signal, the sampled inverse data signal provided in response to said at least one clock signal and said at least one data signal. The storage unit comprises a first and a second storage nodes configured to receive and store the sampled data signal and the sampled inverse data signal. The storage unit comprises drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. The buffer unit provides an output sampled data signal as received from the storage unit.

摘要翻译： 触发器电路具有对辐射诱导的软错误的改进的鲁棒性。 触发器单元包括以下元件。 用于接收至少一个数据信号和至少一个时钟信号的传送单元，耦合到传送单元的存储单元和耦合到存储单元的缓冲单元。 传送单元包括适于接收所述至少一个数据信号和所述至少一个时钟信号的多个输入节点; 第一输出节点，用于响应于所述至少一个时钟信号和所述至少一个数据信号提供采样数据信号; 以及用于提供采样的反向数据信号的第二输出节点，响应于所述至少一个时钟信号和所述至少一个数据信号而提供的采样的反向数据信号。 存储单元包括被配置为接收和存储采样的数据信号和采样的反向数据信号的第一和第二存储节点。 存储单元包括被配置为选择性地将第一和第二存储节点之一耦合到地的驱动晶体管; 被配置为选择性地将第一和第二存储节点中的另一个耦合到电源的负载晶体管; 以及至少一个稳定器晶体管，被配置为提供对应的冗余存储节点并限制所述第一和第二存储节点之间的反馈，所述冗余存储节点在软错误的情况下能够恢复所述第一或第二存储节点。 缓冲单元提供从存储单元接收的输出采样数据信号。

公开(公告)号：US07583555B2

公开(公告)日：2009-09-01

申请号：US10814935

申请日：2004-03-30

申请人： Inyup Kang ,  Karthikeyan Ethirajan ,  Matthew Levi Severson ,  Mohamed Elgebaly ,  Manoj Sachdev ,  Amr Fahim

发明人： Inyup Kang ,  Karthikeyan Ethirajan ,  Matthew Levi Severson ,  Mohamed Elgebaly ,  Manoj Sachdev ,  Amr Fahim

IPC分类号： G11C7/00 ,  G05F1/40

CPC分类号： G05F1/40 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage. In one embodiment, the closed-loop circuit includes a critical path replica for providing estimated frequencies of operation necessary for a critical path in the integrated circuit device. A ring oscillator circuit may be used in one embodiment in the critical path and/or in the open loop circuit.

摘要翻译： 一方面，用于电压调节的方法和装置在一个方面使用特定于所讨论的集成器件的工艺分裂的最坏情况的电源电压。 在另一方面，两相电压调节系统和方法识别与第一阶段中的集成电路器件系列相关的特征数据，并且识别在第二阶段中候选集成电路器件的相关联的工艺分组。 然后使用来自第一阶段的表征数据来提供对应于候选设备的目标操作频率的电源电压。 另一方面，混合电压调节器电路包括开环电路，其自动识别集成电路器件的工艺分离，并且允许调节器基于该工艺分离特有的特性数据修改供电电压，以及闭环电路 调节电源电压。 在一个实施例中，闭环电路包括关键路径副本，用于提供集成电路设备中的关键路径所需的估计工作频率。 在一个实施例中，在关键路径和/或开环电路中可以使用环形振荡器电路。