公开(公告)号：US06665207B2

公开(公告)日：2003-12-16

申请号：US09992203

申请日：2001-11-14

申请人： Phillip G. Wald ,  Casey Kurth ,  Scott Derner

发明人： Phillip G. Wald ,  Casey Kurth ,  Scott Derner

IPC分类号： G11C1124

CPC分类号： H01L27/10894 ,  G11C17/12 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852 ,  H01L27/112 ,  H01L27/11213 ,  H01L28/84

摘要： A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.

公开(公告)号：US06603693B2

公开(公告)日：2003-08-05

申请号：US10017868

申请日：2001-12-12

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C702

CPC分类号： G11C7/14 ,  G11C11/4099

摘要： A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. The reference circuitry can be an un-programmed DRAM cell, a non-volatile ROM memory cell or a conductor coupled to a reference voltage.

摘要翻译： DRAM使用偏置或参考电路来提高单元读取余量。 参考电路耦合到互补数字线，以利用有源数字线来提高差分电压。 一个实施例，通过减少补充数字线电压来提高余量。 参考电路可以是未编程的DRAM单元，非易失性ROM存储器单元或耦合到参考电压的导体。

公开(公告)号：US06501188B1

公开(公告)日：2002-12-31

申请号：US08887547

申请日：1997-07-03

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L23544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

公开(公告)号：US06407455B1

公开(公告)日：2002-06-18

申请号：US09612677

申请日：2000-07-10

申请人： Phillip G. Wald ,  Kunal R. Parekh

发明人： Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L2352

CPC分类号： H01L21/76895 ,  H01L21/76807 ,  H01L2221/1063

摘要： A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

摘要翻译： 一种半导体器件，包括具有形成在该结构的上表面的上表面和接触表面的结构。 在接触表面上形成绝缘材料，并且导电流道在有源区域上延伸，使得导电流道的下表面在有效区域之上并与活性区域分离。 在导电流道中形成加宽部分，其中开口形成在加宽部分中并与加宽部分的边缘自对准。 导电柱与开口自对准，并通过开口向下穿过绝缘材料延伸至有源区。 导电流道提供局部互连，其可以被布置在结构上和结构上形成的器件特征上，而不使用附加的金属层。

公开(公告)号：US06391805B1

公开(公告)日：2002-05-21

申请号：US09653120

申请日：2000-08-31

申请人： Richard H. Lane ,  Phillip G. Wald

发明人： Richard H. Lane ,  Phillip G. Wald

IPC分类号： C23F100

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/324 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/904 ,  Y10S438/908

摘要： This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

公开(公告)号：US06387828B1

公开(公告)日：2002-05-14

申请号：US09654029

申请日：2000-08-31

申请人： Richard H. Lane ,  Phillip G. Wald

发明人： Richard H. Lane ,  Phillip G. Wald

IPC分类号： H01L21283

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/324 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/904 ,  Y10S438/908

摘要： This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

公开(公告)号：US6144109A

公开(公告)日：2000-11-07

申请号：US502925

申请日：2000-02-11

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： G03F9/00 ,  H01L23/544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

公开(公告)号：US6096626A

公开(公告)日：2000-08-01

申请号：US146732

申请日：1998-09-03

申请人： Keith Smith ,  Phillip G. Wald

发明人： Keith Smith ,  Phillip G. Wald

IPC分类号： H01L21/205 ,  H01L21/285 ,  H01L21/768 ,  H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/76877

摘要： In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C. In another aspect, the invention includes a semiconductor processing method comprising, in an uninterrupted deposition process, depositing a silicon layer which comprises an essentially amorphous silicon region, an essentially polycrystalline silicon region, and a transition region interconnecting the essentially amorphous silicon region and the essentially polycrystalline silicon region, the essentially amorphous silicon region having an amorphous silicon content which is greater than or equal to about 90 weight percent of a total material of the amorphous silicon region, the essentially polycrystalline silicon region having a polycrystalline silicon content which is greater than or equal to about 90 weight percent of a total material of the polycrystalline silicon region, the transition comprising an amorphous silicon content and a polycrystalline silicon content, the transition region being defined as a region having both a lower amorphous silicon content than the essentially amorphous silicon region and a lower polycrystalline silicon content than the essentially polycrystalline silicon region, the transition region being at least 45 Angstroms thick.

摘要翻译： 在一个方面，本发明包括一种半导体处理方法，包括在不同的沉积温度下在衬底上沉积硅层，其至少包括将沉积温度提高到约550℃至约560℃的范围。另一方面 本发明包括半导体处理方法，其包括在不间断的沉积工艺中沉积硅层，该硅层包括基本上非晶硅区域，基本上多晶硅区域和将基本上非晶硅区域和基本上多晶硅区域互连的过渡区域 ，所述非晶硅区域的非晶硅含量大于或等于所述非晶硅区域的总材料的约90重量％，所述多晶硅区域的多晶硅含量大于或等于约 90 所述多晶硅区域的总材料的百分比，所述过渡包括非晶硅含量和多晶硅含量，所述过渡区域被定义为具有比所述基本上非晶硅区域低的非晶硅含量的区域，以及下部多晶硅层 硅含量高于基本上多晶硅的区域，该过渡区域至少为45埃厚。

公开(公告)号：US5238862A

公开(公告)日：1993-08-24

申请号：US854435

申请日：1992-03-18

申请人： Guy Blalock ,  Phillip G. Wald

发明人： Guy Blalock ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

摘要： A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

摘要翻译： 在半导体晶片上形成电容器的方法包括：a）在干式蚀刻反应器中，利用选择的反应性气体组分的气体流速，选择性地各向异性地将具有最小选定开口尺寸的电容器接触开口刻蚀成绝缘介电层;以及 惰性气体轰击组分，轰击组分的流速显着超过反应组分的流速，以有效地产生具有沟槽条纹侧壁的电容器接触开口，从而限定母电容器接触开口条纹; b）在条纹电容器接触开口内提供导电存储节点材料层; c）去除所述导电材料层的至少一部分以在所述绝缘电介质内限定具有条纹侧壁的隔离电容器存储节点; d）相对于导电材料选择性地蚀刻绝缘介电层，足以露出至少一部分外部凸纹状导电材料侧壁; 以及e）在蚀刻的导电材料的顶部和其暴露的条纹侧壁上提供电容器电介质和电容器电池材料的保形层。 本发明还包括具有具有向上升高的外侧壁的导电存储节点的堆叠电容器结构。 这样的侧壁具有纵向延伸的条纹，以在最终结构中最大化表面积和相应的电容。

公开(公告)号：US5030587A

公开(公告)日：1991-07-09

申请号：US534126

申请日：1990-06-05

申请人： Phillip G. Wald ,  Pierre Fazan

发明人： Phillip G. Wald ,  Pierre Fazan

IPC分类号： H01L21/768

CPC分类号： H01L21/768 ,  H01L21/76819 ,  H01L21/76885

摘要： A method of forming digit lines on a semiconductor wafer having integrated circuits comprises the following consecutive steps:selectively processing the wafer to produce a desired array of dynamic random access memory cells having associated word lines and exposed active areas, the word lines being defined by electrically conductive regions comprised of a polysilicon/high conductive material sandwich structure and having side and top electrically insulated regions comprised of oxide;providing a layer of doped epitaxial monocrystalline silicon atop exposed active areas to a height which is below the uppermost portions of the electrically insulated regions atop the word lines, and above the height of the uppermost portions of the word line electrically conductive regions;providing a layer of electrically insulating oxide atop the wafer, the electrically insulating layer having a lowest point which is higher than the height of the doped epitaxial silicon layer;planarizing the electrically insulating layer by removing electrically insulating material to provide a substantially planar upper layer of electrically insulating material at a height which is substantially coincident with a common height of the uppermost portions of the tops of the electrically insulated regions of the word lines;etching vias into the electrically insulating layer which generally align with doped epitaxial silicon;depositing an electrically conductive doped polysilicon layer atop the planarized and etched electrically insulating oxide layer; andetching the doped polysilicon layer to form desired substantially planar digit lines.

摘要翻译： 在具有集成电路的半导体晶片上形成数字线的方法包括以下连续步骤：选择性地处理晶片以产生具有相关联的字线和暴露的有源区的期望阵列的动态随机存取存储器单元，字线由电 导电区域由多晶硅/高导电材料夹层结构构成，并且具有由氧化物组成的侧面和顶部电绝缘区域; 在暴露的有源区域之上提供一层掺杂的外延单晶硅，该层高于在字线顶部的绝缘区域的最上部以及字线导电区域的最上部的高度以下的高度; 在所述晶片顶上提供一层电绝缘氧化物，所述电绝缘层的最低点高于所述掺杂的外延硅层的高度; 通过去除电绝缘材料来平坦化电绝缘层，以在与字线的电绝缘区域的顶部的最上部的公共高度基本一致的高度提供基本平坦的电绝缘材料上层; 将通孔蚀刻到通常与掺杂的外延硅对准的电绝缘层中; 在平坦化和蚀刻的电绝缘氧化物层的顶部沉积导电掺杂多晶硅层; 并蚀刻掺杂多晶硅层以形成所需的基本上平面的数字线。