公开(公告)号：US6054364A

公开(公告)日：2000-04-25

申请号：US149700

申请日：1998-09-08

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： The present invention is directed to am improved chemical mechanical polish etch stop for a trench isolation and a method for making same. The method comprises forming at least four process layers above a surface of a semiconducting substrate. The method further comprises patterning said plurality of process layers to define an opening exposing a portion of the surface of the substrate. A trench is formed in the substrate, and the trench and the opening are then filled with a dielectric material. The surface of the dielectric material and the surface of the top process layer are then planarized. The present inventive structure is comprised of at least four process layers positioned above a substrate, an opening formed in said plurality of layers, a trench formed in said substrate, and a dielectric material positioned in said opening and said.

摘要翻译： 本发明涉及用于沟槽隔离的改进的化学机械抛光蚀刻停止及其制造方法。 该方法包括在半导体衬底的表面上方形成至少四个工艺层。 该方法还包括图案化所述多个处理层以限定露出衬底表面的一部分的开口。 在衬底中形成沟槽，然后用介电材料填充沟槽和开口。 然后将电介质材料的表面和顶部工艺层的表面平坦化。 本发明的结构包括位于衬底上方的至少四个工艺层，形成在所述多个层中的开口，在所述衬底中形成的沟槽，以及定位在所述开口中的电介质材料。

公开(公告)号：US6005274A

公开(公告)日：1999-12-21

申请号：US163966

申请日：1998-09-30

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.

摘要翻译： 本发明涉及一种新的半导体器件及其制造方法。 该半导体器件由位于栅介电层和导体层之间的栅介电层，导体层和金属氧化物层构成。 该方法包括在栅极介电层和导体层之间形成栅极电介质层，导体层和金属氧化物层。

公开(公告)号：US5976952A

公开(公告)日：1999-11-02

申请号：US812320

申请日：1997-03-05

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76213

摘要： A semiconductor process in which oxygen is selectively implanted into isolation regions of a semiconductor substrate and subsequently annealed to form isolation structures within the isolation regions. Preferably, a semiconductor substrate is provided and a pad oxide layer is deposited on the semiconductor substrate. A barrier layer is then deposited on the pad oxide layer and a photoresist layer is formed over the barrier layer and patterned to form a photoresist mask. The photoresist mask is aligned over active regions of the semiconductor substrate. An oxygen bearing species is then introduced to an isolation region of the semiconductor substrate. The isolation region is laterally displaced between the active regions. The introducing of the oxygen bearing species into the isolation region results in the formation of an oxygenated region of the semiconductor substrate. Thereafter, the semiconductor substrate is annealed to react the oxygen bearing species with the semiconductor substrate atoms within the isolation region thereby forming an isolation oxide within the isolation region. The introduction of the oxygen bearing species into the semiconductor substrate preferably is accomplished by implanting oxygen ions into the substrate. In one embodiment the annealing of the semiconductor substrate is accomplished by immersing the semiconductor substrate in an ambient maintained at a temperature in the range of approximately 600.degree. C. to 900.degree. C. for a duration in the range of approximately 2 to 20 minutes. In another embodiment, the annealing the semiconductor substrate is accomplished during subsequent fabrication processing such that the annealing requires no dedicated processing step.

摘要翻译： 一种半导体工艺，其中将氧选择性地注入到半导体衬底的隔离区域中，随后退火以在隔离区内形成隔离结构。 优选地，提供半导体衬底并且在半导体衬底上沉积衬垫氧化物层。 然后在衬垫氧化物层上沉积阻挡层，并在阻挡层上形成光致抗蚀剂层，并将其图案化以形成光刻胶掩模。 光致抗蚀剂掩模在半导体衬底的有源区上对准。 然后将含氧物质引入半导体衬底的隔离区域。 隔离区域在有源区域之间横向移位。 将含氧物质引入隔离区域导致半导体衬底的氧化区域的形成。 此后，将半导体衬底退火以使含氧物质与隔离区域内的半导体衬底原子反应，从而在隔离区域内形成隔离氧化物。 将含氧物质引入半导体衬底中优选通过将氧离子注入到衬底中来实现。 在一个实施例中，半导体衬底的退火是通过将半导体衬底浸入保持在约600℃至900℃范围内的温度的环境中，持续约2至20分钟的范围来完成的。 在另一个实施例中，在随后的制造处理期间完成半导体衬底的退火，使得退火不需要专门的处理步骤。

公开(公告)号：US5943596A

公开(公告)日：1999-08-24

申请号：US927097

申请日：1997-08-29

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28114 ,  H01L29/517 ,  H01L29/66583 ,  H01L29/78391 ,  H01L29/4975

摘要： A semiconductor device having a gate electrode stack formed using a patterned oxide layer is disclosed. The device is formed by forming an oxide layer over a surface of a substrate and forming at least one opening in the oxide layer. A high permittivity plug (e.g., a BST plug) is formed in the lower portion of the opening. A conductive plug (e.g., a metal silicide plug) is formed in an upper portion of the opening over the high permittivity plug. Remaining portions of the oxide layer are then removed. The conductive plug and high permittivity plug may form a gate electrode and a gate insulating layer, respectively.

摘要翻译： 公开了一种具有使用图案化氧化物层形成的栅电极堆叠的半导体器件。 该器件通过在衬底的表面上形成氧化物层并在氧化物层中形成至少一个开口而形成。 在开口的下部形成有高介电常数的插塞（例如，BST插头）。 导电插头（例如，金属硅化物插塞）形成在高介电常数插头上的开口的上部。 然后除去氧化物层的剩余部分。 导电插塞和高电容率插头可分别形成栅电极和栅极绝缘层。

公开(公告)号：US6165314A

公开(公告)日：2000-12-26

申请号：US588910

申请日：2000-06-07

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/00

CPC分类号： H01L21/67069

摘要： The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.

摘要翻译： 本发明涉及一种减小加工层厚度的方法和装置。 该方法包括产生由活性离子组成的相对高速气流，该活性离子将与处理层反应，并相对于喷嘴移动晶片以实现工艺层厚度的减小。 该装置包括处理室，用于将晶片固定在腔室中的装置，具有出口的喷嘴，该出口的宽度基本上与位于腔室中的晶片的直径相同。 该装置还包括用于相对于喷嘴移动晶片的装置。

公开(公告)号：US6152075A

公开(公告)日：2000-11-28

申请号：US143605

申请日：1998-08-31

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： C23C16/44 ,  C23C16/458 ,  C23C16/46 ,  C23C16/48 ,  C23C16/511 ,  C23C16/00

CPC分类号： C23C16/4409 ,  C23C16/4588 ,  C23C16/46 ,  C23C16/483 ,  C23C16/511

摘要： The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber having a wafer position at which a wafer can be placed during chemical wafer deposition processing, and a source of reactive gases for providing reactive gases to the chemical vapor deposition chamber. This system also includes a coherent radiation source for directing a beam of coherent radiation toward the wafer position, and a shield positioned between the coherent radiation source and the wafer position. This shield is adapted to distribute energy from the beam of coherent radiation across the wafer when the wafer is located at the wafer position.

摘要翻译： 本公开涉及一种化学气相沉积系统，该化学气相沉积系统包括化学气相沉积室，该化学气相沉积室具有在化学晶片沉积处理期间可以放置晶片的晶片位置，以及用于向化学气相沉积室提供反应气体的反应气体源。 该系统还包括用于将相干辐射束引向晶片位置的相干辐射源，以及位于相干辐射源和晶片位置之间的屏蔽。 当晶片位于晶片位置时，该屏蔽适于将来自相干辐射束的能量分布在晶片上。

公开(公告)号：US6124172A

公开(公告)日：2000-09-26

申请号：US163688

申请日：1998-09-30

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L21/331 ,  H01L21/335

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/6659

摘要： A method of making a semiconductor device includes forming gate electrode over a substrate and a protective layer over the gate electrode. A portion of the protective layer is selectively removed to expose a peripheral region of the gate electrode. A remainder of the protective layer remains disposed over a central region of the gate electrode. An upper portion of the peripheral region of the gate electrode is then removed typically leaving an underlying portion. Often, a dopant material is implanted into the substrate adjacent to and beneath the underlying portion to simultaneously form lightly-doped and heavily-doped regions beneath and adjacent to the underlying portion, respectively. In addition, all or part of the underlying portion may be oxidized to provide a gate electrode with reduced width.

摘要翻译： 制造半导体器件的方法包括在栅极上方形成栅电极和保护层。 选择性地去除保护层的一部分以露出栅电极的外围区域。 保护层的其余部分保持设置在栅电极的中心区域上方。 然后通常离开底层部分去除栅电极的周边区域的上​​部。 通常，将掺杂剂材料注入到与底层部分相邻并且在下面部分附近的衬底中，以分别在下面部分和下面部分形成轻掺杂和重掺杂区域。 此外，底层部分的全部或部分可以被氧化以提供具有减小的宽度的栅电极。

公开(公告)号：US6106618A

公开(公告)日：2000-08-22

申请号：US88783

申请日：1998-06-01

申请人： Mark C. Gilmer ,  Mark I. Gardner

发明人： Mark C. Gilmer ,  Mark I. Gardner

IPC分类号： B05B9/04 ,  B05B13/02 ,  B05C9/14 ,  B05C11/08 ,  G03F7/16 ,  H01L21/00 ,  B05C11/02 ,  B05B3/02 ,  B05C9/06 ,  B05C13/00

CPC分类号： H01L21/6715 ,  B05B13/0228 ,  B05C11/08 ,  G03F7/162 ,  B05B9/0403 ,  B05C9/14

摘要： Apparatus and method for depositing fluids on both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel and that is operable to rotate the mandrel. The apparatus also includes means for dispensing a first volume of fluid on the semiconductor wafer and a second volume of fluid on the semiconductor wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel. The mandrel is rotated to spin the semiconductor wafer and a semiconductor processing fluid is sprayed on the first and second sides of the semiconductor wafer.

摘要翻译： 提供了用于在具有中心开口的半导体晶片的两侧上沉积流体的装置和方法。 在一个方面，该装置包括用于保持晶片的心轴和联接到心轴的马达，并且可操作以用于旋转心轴。 该装置还包括用于在半导体晶片上分配第一体积的流体的装置和半导体晶片上的第二体积的流体。 根据该方法，将半导体晶片连接到可旋转心轴。 旋转心轴以旋转半导体晶片，并且半导体处理流体喷射在半导体晶片的第一和第二侧上。

公开(公告)号：US6057584A

公开(公告)日：2000-05-02

申请号：US994302

申请日：1997-12-19

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  H. Jim Fulford ,  Jack C. Lee

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  H. Jim Fulford ,  Jack C. Lee

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583 ,  H01L21/2822 ,  H01L21/28229

摘要： A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.

摘要翻译： 具有栅绝缘三层的半导体器件包括衬底，设置在衬底上的含氮层，设置在含氮层上的第一介电层，设置在第一介电层上的第二电介质层和栅电极 设置在第二电介质层上。 使用介电常数为4〜100的氧化物形成第一和第二电介质层中的一个，并且使用介电常数介于10〜10000的氧化物形成第一和第二电介质层中的另一个。

公开(公告)号：US6051865A

公开(公告)日：2000-04-18

申请号：US189352

申请日：1998-11-09

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Derick J. Wristers

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L21/26506

摘要： A transistor and a method for making a transistor are described. Barrier species such as nitrogen may be introduced into a semiconductor substrate to form a barrier layer. A dielectric having a high dielectric constant, preferably a metal- and oxygen-bearing dielectric, may then be deposited upon the semiconductor substrate. The barrier layer preferably mitigates short channel effects and prevents dopant and/or metal atom migration into or out of the gate structure. The dielectric may be annealed in an oxygen-bearing atmosphere to passivate the dielectric material and to incorporate barrier species into the dielectric. Alternatively, the anneal may be performed in an inert atmosphere. Following deposition of a conductive gate material upon the dielectric, a gate conductor and gate dielectric may be patterned. Lightly doped drain impurity areas and/or source and drain impurity areas may then be formed in the semiconductor substrate.

摘要翻译： 描述晶体管和制造晶体管的方法。 可以将诸如氮的阻挡物质引入到半导体衬底中以形成阻挡层。 然后可以在半导体衬底上沉积具有高介电常数的电介质，优选含金属和含氧电介质。 阻挡层优选地减轻短沟道效应并防止掺杂物和/或金属原子迁移进入或离开栅极结构。 电介质可以在含氧气氛中进行退火以钝化介电材料并将阻挡物质并入电介质中。 或者，退火可以在惰性气氛中进行。 在导电栅极材料沉积在电介质上之后，栅极导体和栅极电介质可以被图案化。 然后可以在半导体衬底中形成轻掺杂漏极杂质区域和/或源极和漏极杂质区域。