公开(公告)号：US20050079714A1

公开(公告)日：2005-04-14

申请号：US10943017

申请日：2004-09-17

申请人： Teng-Wang Huang ,  Kristin Schupke

发明人： Teng-Wang Huang ,  Kristin Schupke

IPC分类号： C23F1/24 ,  H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/31111 ,  H01L21/30608

摘要： A method for etching Si anisotropically uses a solution containing NH4F and HF.

摘要翻译： 各向异性蚀刻Si的方法使用含NH4F和HF的溶液。

公开(公告)号：US08835318B2

公开(公告)日：2014-09-16

申请号：US13414946

申请日：2012-03-08

申请人： Clemens Fitz ,  Jochen Poth ,  Kristin Schupke

发明人： Clemens Fitz ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L21/283 ,  H01L23/532

CPC分类号： H01L21/02068 ,  H01L21/28518 ,  H01L21/76829 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.

摘要翻译： 通过在SWC工具中应用HNO3代替SPM清洗工艺，可以消除Ni和Pt残留物。 实施例包括在半导体衬底上沉积一层Ni / Pt，对沉积的Ni / Pt层进行退火，通过在SWC工具中对退火的Ni / Pt层施加HNO 3，从退火的Ni / Pt层去除未反应的Ni，退火Ni 去除Ni / Pt层，并从退火的Ni去除的Ni / Pt层去除未反应的Pt。 实施例包括在基板上形成第一和第二栅极电极，在每个栅电极的相对侧上形成间隔物，并在邻近每个间隔物的衬底上形成含Pt的NiSi，蚀刻间隔物，在第一栅电极上形成拉伸应变层， 在SWC工具中的第一HNO 3，在第二栅电极上形成压应变层，并在SWC工具中施加第二HNO 3。

公开(公告)号：US20060079049A1

公开(公告)日：2006-04-13

申请号：US11223800

申请日：2005-09-09

申请人： Srivatsa Kundalgurki ,  Peter Moll ,  Dirk Manger ,  Kristin Schupke ,  Till Schloesser

发明人： Srivatsa Kundalgurki ,  Peter Moll ,  Dirk Manger ,  Kristin Schupke ,  Till Schloesser

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

摘要： In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).

摘要翻译： 在制造包括电极结构（80）的电容器的方法中，辅助层（40）形成在衬底（10）上。 确定电极结构（80）的形状的凹部（60）被蚀刻到辅助层（40）中，电容器的电极结构形成在凹部中。 作为示例，辅助层可以是半导体层（40）。

公开(公告)号：US07018781B2

公开(公告)日：2006-03-28

申请号：US10811509

申请日：2004-03-29

申请人： Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

发明人： Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC分类号： G03F7/00

CPC分类号： H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

摘要： Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

摘要翻译： 公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。 可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

公开(公告)号：US20050221620A1

公开(公告)日：2005-10-06

申请号：US10814570

申请日：2004-03-31

申请人： Teng-Wang Huang ,  Kristin Schupke

发明人： Teng-Wang Huang ,  Kristin Schupke

IPC分类号： H01L21/302 ,  H01L21/306

CPC分类号： H01L21/30608

摘要： The invention relates to a process for etching at least one substrate, in particular at least one silicon wafer for the fabrication of DRAM memory chips. The process comprising at least one substrate, for a first etching step, is arranged for a predetermined time in a first vessel containing a first etchant, then at least one substrate, for a first rinsing step, is arranged for a predetermined time in a second vessel containing a first rinsing agent, the first rinsing agent containing at least one wetting agent, and then at least one substrate, for a second etching step, is arranged for a predetermined time in a third vessel containing a second etchant.

摘要翻译： 本发明涉及用于蚀刻至少一个衬底，特别是用于制造DRAM存储器芯片的至少一个硅晶片的工艺。 包括至少一个用于第一蚀刻步骤的衬底的方法在包含第一蚀刻剂的第一容器中布置预定时间，然后在第二冲洗步骤中将至少一个衬底布置在预定时间内 含有第一冲洗剂的容器，含有至少一种润湿剂的第一冲洗剂，然后在第二蚀刻步骤中，至少一个基材，在包含第二蚀刻剂的第三容器中布置预定时间。

公开(公告)号：US06734077B2

公开(公告)日：2004-05-11

申请号：US10234547

申请日：2002-09-04

申请人： Matthias Förster ,  Kristin Schupke ,  Anja Morgenschweis ,  Anett Moll ,  Jens-Uwe Sachse

发明人： Matthias Förster ,  Kristin Schupke ,  Anja Morgenschweis ,  Anett Moll ,  Jens-Uwe Sachse

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L28/84

摘要： A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.

摘要翻译： 一种制造用于半导体存储器的沟槽电容器的方法包括在设置在衬底中的沟槽中形成掩模层。 用于图案化掩模层的纳米晶体沉积在掩模层上。 通过图案化的掩模层，在沟槽的下部区域中将微螺旋线蚀刻到衬底中。 微通道形成粗糙的沟槽侧壁。 结果，外部电容器电极形成有更大的表面积，允许沟槽电容器具有较高的电容。

公开(公告)号：US20130234213A1

公开(公告)日：2013-09-12

申请号：US13415492

申请日：2012-03-08

申请人： Sivakumar KUMARASAMY ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

发明人： Sivakumar KUMARASAMY ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L21/66 ,  H01L29/68

CPC分类号： H01L21/28518 ,  H01L22/12 ,  H01L22/20

摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.

摘要翻译： 如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。 实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。 可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

公开(公告)号：US07615444B2

公开(公告)日：2009-11-10

申请号：US11477581

申请日：2006-06-29

申请人： Odo Wunnicke ,  Peter Moll ,  Kristin Schupke

发明人： Odo Wunnicke ,  Peter Moll ,  Kristin Schupke

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10808 ,  H01L27/10852

摘要： A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

摘要翻译： 一种用于形成电容器结构的方法，根据该方法执行以下连续步骤：提供在其表面上具有接触焊盘的基板和设置有至少一个沟槽的介电模，留下暴露的接触焊盘; 在所述沟槽的顶部区域中在所述沟槽的侧壁上形成第一导电层，所述导电层不与所述接触焊盘接触; 沉积第一介电层; 在所述接触焊盘和所述沟槽的侧壁上沉积第二导电层; 沉积第二电介质层; 沉积第三导电层; 以及形成互连所述第一导电层和所述第三导电层的垂直插头。

公开(公告)号：US07078748B2

公开(公告)日：2006-07-18

申请号：US10865763

申请日：2004-06-14

申请人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

发明人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

IPC分类号： H01L27/148

CPC分类号： H01L21/28044

摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

摘要翻译： 通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中， 过渡金属是钛，钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

公开(公告)号：US20050003308A1

公开(公告)日：2005-01-06

申请号：US10811509

申请日：2004-03-29

申请人： Hans-Georg Frohlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

发明人： Hans-Georg Frohlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  G03F7/00

CPC分类号： H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

摘要： In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductor surface and, finally, the contact opening regions are filled with a conductive material.

摘要翻译： 为了在具有选择晶体管的存储单元的布置的存储器模块中制造接触孔平面，在半导体衬底上具有半导体表面上相互邻近的栅极电极轨迹的布置，在半导体上形成绝缘体层 表面和牺牲层随后形成在绝缘体层上，然后在牺牲层上产生材料插塞以便限定相互相邻的栅极电极轨道之间的接触开口，牺牲层被蚀刻以形成具有下面牺牲的材料塞 在玻璃质层的生产之后，在相邻的栅电极轨道之间的接触开口上方露出牺牲层块，形成基本平坦的表面，然后从玻璃质层蚀刻牺牲层材料，并且 未覆盖的绝缘体材料在触点上方移除 并且最后，用导电材料填充接触开口区域。