公开(公告)号：US5917354A

公开(公告)日：1999-06-29

申请号：US868974

申请日：1997-06-04

申请人： Hiroaki Nakai ,  Shinichi Kobayashi ,  Masaaki Mihara

发明人： Hiroaki Nakai ,  Shinichi Kobayashi ,  Masaaki Mihara

IPC分类号： G11C5/14 ,  G11C11/407 ,  G11C16/06 ,  H01L27/115 ,  H01L29/68 ,  H03K17/20

CPC分类号： G11C5/143 ,  Y10T307/675 ,  Y10T307/735

摘要： When a state of outputting a third power supply potential to an output node is switched to a state of outputting a second power supply potential, connection between a supply unit of the second power supply potential and the output node is made through a first P-channel MOSFET. Further, when the first P-channel MOSFET is turned off, i.e., when the third power supply potential is output to the output node, the third power supply potential is also applied to a gate of the first P-channel MOSFET. Therefore, even when the potential of the output node rises to the third power supply potential, this transistor is not turned on. Thus, the second power supply potential and the output node are appropriately and electrically isolated from each other. The circuit can be used with a flash memory to prevent over programming.

摘要翻译： 当向输出节点输出第三电源电位的状态切换到输出第二电源电位的状态时，第二电源电位的供给单元与输出节点之间的连接通过第一P沟道 MOSFET。 此外，当第一P沟道MOSFET截止时，即当第三电源电位输出到输出节点时，第三电源电位也被施加到第一P沟道MOSFET的栅极。 因此，即使输出节点的电位上升到第三电源电位，该晶体管也不会导通。 因此，第二电源电位和输出节点彼此适当且电气隔离。 该电路可与闪存一起使用，以防止过度编程。

公开(公告)号：US5705895A

公开(公告)日：1998-01-06

申请号：US572664

申请日：1995-12-14

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： G04G19/02 ,  G04G9/00 ,  H02M7/48 ,  H02M7/538 ,  H05B33/08 ,  H05B37/02

CPC分类号： H05B33/08 ,  Y02B20/325 ,  Y10S315/05

摘要： A power terminal is connected to a DC power source. A differential amplifier has primary and secondary input terminals and an output terminal, and a device applies a reference voltage to the secondary input terminal of the differential amplifier. A phase inverter has an input terminal connected to the output terminal of the differential amplifier and has primary and secondary output terminals that output two output signals of opposite phase. A push-pull drive circuit has primary and secondary input terminals connected to the primary and secondary output terminals of the phase inverter, and has primary and secondary output terminals connected to a switching element that alternately turns on and off by being driven by the two output signals of opposite phase that are provided from the output terminals of the phase inverter. An autotransformer has a tap connected to the power terminal and taps, provided at both sides of the tap connected to the power terminal, that are connected to the primary and secondary output terminals at the push-pull drive circuit, respectively. A capacitive load may be connected at both sides of the autotransformer. A positive feedback path connects one terminal of the autotransformer to the primary input terminal of the differential amplifier, and a sinusoidal AC voltage is applied to the capacitive load. A duty ratio conversion circuit automatically changes the duty ratio of drive signals for the push-pull drive circuit according to the resonance frequency that is determined by the inductance of the autotransformer and the capacitance of the capacitive load. The duty ratio conversion circuit is connected between the phase inverter and the push-pull drive circuit.

摘要翻译： 电源端子连接到直流电源。 差分放大器具有一次和二次输入端子和一个输出端子，并且器件将参考电压施加到差分放大器的次级输入端子。 一个相位逆变器的输入端连接到差分放大器的输出端，并具有输出相反相位的两个输出信号的初级和次级输出端。 推挽驱动电路具有连接到相位逆变器的主输出端和次输出端的初级和次级输入端，并且具有连接到开关元件的初级和次级输出端子，其通过由两个输出驱动而交替地导通和关断 从相变器的输出端子提供的反相信号。 自耦变压器具有连接到电源端子的抽头和分别连接到电源端子的抽头两侧的抽头，分别连接到推挽驱动电路的主输出端和次输出端。 电容性负载可以连接在自耦变压器的两侧。 正反馈路径将自耦变压器的一个端子连接到差分放大器的主输入端，并且正弦交流电压被施加到电容性负载。 占空比转换电路根据由自耦变压器的电感和容性负载的电容确定的谐振频率自动改变推挽驱动电路的驱动信号的占空比。 占空比转换电路连接在相位逆变器和推挽驱动电路之间。

公开(公告)号：US5130945A

公开(公告)日：1992-07-14

申请号：US551268

申请日：1990-07-12

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04 ,  G11C15/043

摘要： Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.

摘要翻译： 每个匹配线连接到构成CAM阵列的多个CAM单元。 当通过字线选择时，相应的CAM单元存储在其数据存储部分中通过位线和反相位线施加的数据。 将存储的数据应用于数据比较部分，以与通过位线和反向位线施加的检索数据进行比较，从而检测它们之间的匹配或失配。 数据比较部分的比较结果首先以电荷的形式存储在电容元件中。 为了防止存储在电容元件中的信息的逸出，阻塞装置阻挡电容元件的充电和放电路径的一部分。 当在电容元件中存储不匹配的信息时，设置在电容元件和匹配线之间的电荷转移装置将一定量的电荷从两者之一传递到另一个。 这导致匹配线上的电荷电位波动。 匹配线上的电位波动取决于连接到匹配线的多个CAM单元中不匹配的CAM单元的数量。 因此，匹配线上的电位检测允许检测不匹配的CAM单元的数量。

公开(公告)号：US4924220A

公开(公告)日：1990-05-08

申请号：US286922

申请日：1988-11-18

申请人： Masaaki Mihara ,  Toshifumi Kobayashi

发明人： Masaaki Mihara ,  Toshifumi Kobayashi

IPC分类号： G06F15/16 ,  G06F13/14 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177

CPC分类号： G06F13/14 ,  G06F13/364

摘要： An arbiter circuit is disclosed for processing competing requests for access to a shared resource made simultaneously by two subsystems in a multi-processor system. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates, and functions to block the passage of a subsequent request signal from one subsystem to the SR flip-flop during a predetermined time interval after a request signal from the other subsystem has been supplied to the flip-flop. A result is that the both inputs of the SR flip-flop are not shifted up from the low levels to the high levels at the same time by the simultaneous generation of request signals from both subsystems, thereby eliminating any possibility of the output from the flip-flop floating at an intermediate level between the high and low level.

摘要翻译： 公开了一种仲裁器电路，用于处理在多处理器系统中由两个子系统同时进行的对共享资源的访问的竞争请求。 仲裁器电路包括由一对NAND门组成的SR触发器，并且在来自另一个子系统的请求信号之后的预定时间间隔期间阻止后续请求信号从一个子系统到SR触发器的通过 已被提供给触发器。 结果是，通过同时生成来自两个子系统的请求信号，SR触发器的两个输入都不会从低电平向上移动到高电平，从而消除了从翻转的输出的任何可能性 - 浮动在高低位之间的中间水平。

公开(公告)号：US20130174680A1

公开(公告)日：2013-07-11

申请号：US13823193

申请日：2011-06-02

申请人： Masaaki Mihara

发明人： Masaaki Mihara

IPC分类号： F16H19/08

CPC分类号： F16H19/08 ,  Y10T74/1888

摘要： Implementations and techniques are generally disclosed for an actuator comprising: a first element, a second element, a third element, a first joint provided between the first element and the second element, a second joint provided between the second element and the third element, and a motor operably coupled to the first joint and configured such that the second element rotates with respect to the first element about a first rotational axis when the motor rotates, wherein the first joint is operably coupled to the second joint and configured such that the third element can rotate with respect to the second element about a second rotational axis when the motor rotates.

摘要翻译： 通常公开了用于致动器的实现和技术，包括：第一元件，第二元件，第三元件，设置在第一元件和第二元件之间的第一接头，设置在第二元件和第三元件之间的第二接头，以及 电动机，其可操作地联接到所述第一接头并且被配置为使得当所述电动机旋转时，所述第二元件相对于所述第一元件围绕第一旋转轴线旋转，其中所述第一接头可操作地联接到所述第二接头并且被配置为使得所述第三元件 当电动机旋转时，它可相对于第二元件围绕第二旋转轴线旋转。

公开(公告)号：US20120014181A1

公开(公告)日：2012-01-19

申请号：US13205900

申请日：2011-08-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： G11C16/10 ,  G11C16/28 ,  G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US08000137B2

公开(公告)日：2011-08-16

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C16/04

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US07701778B2

公开(公告)日：2010-04-20

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20090244972A1

公开(公告)日：2009-10-01

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C14/00 ,  G11C16/04 ,  G11C7/06

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US07573742B2

公开(公告)日：2009-08-11

申请号：US11550335

申请日：2006-10-17

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。