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241 条记录 (耗时 0.049 秒)

    Analog-to-digital converter including differential pair circuit
    11.
    发明授权
    Analog-to-digital converter including differential pair circuit 失效
    模数转换器包括差分对电路

    公开(公告)号：US08681033B2

    公开(公告)日：2014-03-25

    申请号：US13535118

    申请日：2012-06-27

    申请人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H03F3/45183 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45674 ,  H03K5/2481 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

    摘要翻译： 根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。 每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。 每个比较器包括用于检测两个输入之间的电位差的差分对电路。 差分对电路包括第一和第二电路部分。 第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。 第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。 可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

    Spin MOSFET and reconfigurable logic circuit
    12.
    发明授权
    Spin MOSFET and reconfigurable logic circuit 有权
    旋转MOSFET和可重构逻辑电路

    公开(公告)号：US08637946B2

    公开(公告)日：2014-01-28

    申请号：US13228852

    申请日：2011-09-09

    申请人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

    发明人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

    IPC分类号： H01L29/82

    CPC分类号： H01L43/02 ,  B01D53/1493 ,  B01D53/62 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L28/00 ,  H01L29/0843 ,  H01L29/0895 ,  H01L29/66984 ,  H01L43/10

    摘要： A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

    摘要翻译： 自旋MOSFET包括：设置在半导体衬底上并具有与膜平面垂直的固定磁化方向的第一铁磁层; 设置在所述第一铁磁层上的半导体层，包括与所述第一铁磁层的上表面相对的下表面，与所述下表面相对的上表面，以及与所述下表面和所述上表面不同的侧面; 第二铁磁层，设置在所述半导体层的上表面上，并且具有与膜平面垂直的可变磁化方向; 设置在第二铁磁层上的第一隧道势垒; 设置在第一隧道屏障上的第三铁磁层; 设置在所述半导体层的侧面上的栅极绝缘膜; 以及设置在半导体层的侧面上的栅电极，其间插入有栅极绝缘膜。

    Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array
    13.
    发明授权
    Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array 有权
    使用自旋MOSFET的存储电路，具有存储功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列

    公开(公告)号：US08611143B2

    公开(公告)日：2013-12-17

    申请号：US13403308

    申请日：2012-02-23

    申请人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： G11C11/00

    CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

    摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

    Content addressable memory
    14.
    发明授权
    Content addressable memory 失效
    内容可寻址内存

    公开(公告)号：US08576601B2

    公开(公告)日：2013-11-05

    申请号：US13403398

    申请日：2012-02-23

    申请人： Takao Marukame ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Mizue Ishikawa ,  Yoshiaki Saito ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

    发明人： Takao Marukame ,  Tomoaki Inokuchi ,  Hideyuki Sugiyama ,  Mizue Ishikawa ,  Yoshiaki Saito ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

    IPC分类号： G11C15/02

    CPC分类号： G11C15/02 ,  G11C11/161 ,  G11C15/046 ,  H01L27/228

    摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

    摘要翻译： 一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

    SPIN TRANSISTOR AND MEMORY
    17.
    发明申请
    SPIN TRANSISTOR AND MEMORY 有权
    旋转晶体管和存储器

    公开(公告)号：US20130075843A1

    公开(公告)日：2013-03-28

    申请号：US13526007

    申请日：2012-06-18

    申请人： Tomoaki Inokuchi ,  Takao Marukame ,  Tetsufumi Tanamoto ,  Hideyuki Sugiyama ,  Mizue Ishikawa ,  Yoshiaki Saito

    发明人： Tomoaki Inokuchi ,  Takao Marukame ,  Tetsufumi Tanamoto ,  Hideyuki Sugiyama ,  Mizue Ishikawa ,  Yoshiaki Saito

    IPC分类号： H01L29/82

    CPC分类号： H01L43/08 ,  H01L29/66984

    摘要： A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.

    摘要翻译： 根据实施例的自旋晶体管包括：形成在衬底上并用作源极和漏极之一的第一磁性层; 绝缘膜，其具有面向第一磁性层的上表面的下表面，与下表面相对的上表面，以及不同于下表面和上表面的侧面，绝缘膜形成在第一磁性层的上表面上 第一磁性层，作为通道; 第二磁性层，形成在绝缘膜的上表面上并用作源极和漏极中的另一个; 沿绝缘膜的侧面形成的栅电极; 以及位于绝缘膜的栅极和侧面之间的栅极绝缘膜。

    Nonvolatile memory circuit using spin MOS transistors
    18.
    发明授权
    Nonvolatile memory circuit using spin MOS transistors 有权
    使用自旋MOS晶体管的非易失性存储电路

    公开(公告)号：US08385114B2

    公开(公告)日：2013-02-26

    申请号：US13360904

    申请日：2012-01-30

    申请人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： G11C11/14

    CPC分类号： G11C14/0081

    摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

    摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

    Spin transistor, programmable logic circuit, and magnetic memory
    19.
    发明授权
    Spin transistor, programmable logic circuit, and magnetic memory 有权
    旋转晶体管，可编程逻辑电路和磁存储器

    公开(公告)号：US08264024B2

    公开(公告)日：2012-09-11

    申请号：US13166285

    申请日：2011-06-22

    申请人： Yoshiaki Saito ,  Hideyuki Sugiyama

    发明人： Yoshiaki Saito ,  Hideyuki Sugiyama

    IPC分类号： H01L29/82

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  H01L29/66984 ,  Y10S977/932 ,  Y10S977/933 ,  Y10S977/936

    摘要： A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.

    摘要翻译： 自旋晶体管包括具有沟道区，第一区和第二区的非磁性半导体衬底。 通道区域在第一和第二区域之间。 自旋晶体管还包括位于第一区域上方并由沿第一方向磁化的铁磁材料制成的第一导电层; 以及第二导电层，其位于第二区域上方并由在相对于第一方向反平行的第一方向和第二方向中的一个中被磁化的铁磁材料制成。 沟道区域在导电层之间引入电子自旋。 自旋晶体管还包括位于导电层之间并位于沟道区之上的栅电极; 以及位于非磁性半导体衬底和至少一个导电层之间的隧道阻挡膜。

    CONSTRUCTION VEHICLE
    20.
    发明申请
    CONSTRUCTION VEHICLE 有权
    建筑车辆

    公开(公告)号：US20120003070A1

    公开(公告)日：2012-01-05

    申请号：US13257207

    申请日：2010-03-15

    申请人： Mamoru Tochizawa ,  Koji Takahashi ,  Yoshiaki Saito

    发明人： Mamoru Tochizawa ,  Koji Takahashi ,  Yoshiaki Saito

    IPC分类号： E02F9/20 ,  G06F19/00 ,  E02F3/36

    CPC分类号： E02F9/202 ,  E02F9/2253

    摘要： The construction vehicle is provided with an engine, a clutch, a travel device, a work equipment, a drive force setting dial, and a controller that includes: a theoretical value determination unit that determines a theoretical value, for the degree of engagement to make the upper limit value of the drive force equal to a set drive force; an operational state determination unit that determines whether the work equipment is outputting the drive force in a predetermined travel direction; a drive force determination unit that determines whether the drive force is greater than the set drive force; and a degree of engagement reduction unit that, if of operational state determination and of drive force determination are both affirmative, causes the degree of engagement to approach the theoretical value.

    摘要翻译： 施工车辆设置有发动机，离合器，行驶装置，作业设备，驱动力设定拨盘和控制器，该控制器包括：理论值确定单元，用于为了使接合程度确定理论值 驱动力的上限值等于设定的驱动力; 操作状态确定单元，其确定所述工作设备是否在预定的行进方向上输出所述驱动力; 驱动力确定单元，其确定驱动力是否大于设定的驱动力; 以及如果操作状态确定和驱动力确定均为肯定的接合减小单元的程度使得接合程度接近理论值。