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    Semiconductor memory device having segment type word line structure
    12.
    发明授权
    Semiconductor memory device having segment type word line structure 有权
    具有段型字线结构的半导体存储器件

    公开(公告)号：US06452860B2

    公开(公告)日：2002-09-17

    申请号：US09871646

    申请日：2001-06-04

    申请人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Atsushi Takeuchi ,  Toshimi Ikeda ,  Kuninori Kawabata

    发明人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Atsushi Takeuchi ,  Toshimi Ikeda ,  Kuninori Kawabata

    IPC分类号： G11C800

    CPC分类号： G11C5/063

    摘要： A semiconductor memory device has a segment type word line structure and comprises a plurality of main word lines and a plurality of sub word lines which are arranged at different levels. The semiconductor memory device is provided with a memory cell array divided into a plurality of cell array blocks. A plurality of sub row decoder areas, each for selecting one of the sub word lines, are defined between the cell array blocks. A plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines are provided. The first metal wiring lines pass across the sub row decoder areas and the cell array blocks.

    摘要翻译： 半导体存储器件具有段类型的字线结构，并且包括多个主字线和排列在不同电平的多个子字线。 半导体存储器件设置有分成多个单元阵列块的存储单元阵列。 在单元阵列块之间定义多个用于选择一个子字线的子行解码器区域。 提供了通过使用与主字线相同的布线层形成的多个第一金属布线。 第一金属布线穿过子行解码器区域和单元阵列块。

    Process for producing a semiconductor device
    13.
    发明授权
    Process for producing a semiconductor device 失效
    半导体装置的制造方法

    公开(公告)号：US5688712A

    公开(公告)日：1997-11-18

    申请号：US643938

    申请日：1996-05-07

    申请人： Taiji Ema ,  Toshimi Ikeda

    发明人： Taiji Ema ,  Toshimi Ikeda

    IPC分类号： H01L21/8244 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L21/70

    CPC分类号： H01L27/105 ,  H01L27/10817 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/86

    摘要： A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covering the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括具有存储单元区域的半导体衬底和围绕存储单元区域的电路区域，其间插入有边界区域。 第一导电层覆盖存储单元区域并延伸到边界区域上。 第一绝缘层覆盖周围电路区域和第一导电层的延伸部分的一部分。 覆盖第一绝缘层和第一导电层的第二绝缘层。 通过第一绝缘层和第二绝缘层形成通孔。 第二导电层经由通孔与另一导电层电连接，并从存储单元区域延伸到周围电路区域。 还公开了制造半导体器件的工艺。

    Process of producing a semiconductor device in which a height difference between a memory cell area and a peripheral area is eliminated
    14.
    发明授权
    Process of producing a semiconductor device in which a height difference between a memory cell area and a peripheral area is eliminated 失效
    制造其中消除了存储单元区域和外围区域之间的高度差的半导体器件的工艺

    公开(公告)号：US5591659A

    公开(公告)日：1997-01-07

    申请号：US318261

    申请日：1994-10-05

    申请人： Taiji Ema ,  Toshimi Ikeda

    发明人： Taiji Ema ,  Toshimi Ikeda

    IPC分类号： H01L21/8242 ,  H01L21/8244 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/86

    摘要： A semiconductor device comprising: a semiconductor substrate having a memory cell area containing a memory cell composed of a capacitor element, and a peripheral circuit area containing a peripheral circuit for controlling the memory cell; an insulating layer covering the peripheral circuit area and being absent in the memory cell area; protective layers effective in etching of the insulating layer and covering the top surfaces and side surfaces of word line conductor patters and bit line conductor patterns in the memory cell area; a contact hole having a circumference defined by one of the protective layers that covers side surfaces of the word line conductor patterns in the memory cell area, the contact hole extending to a diffused region in the semiconductor substrate; and a storage electrode of the capacitor element being connected to the diffused region through the contact hole. A process of producing the semiconductor device is also disclosed.

    摘要翻译： 一种半导体器件，包括：具有包含由电容器元件构成的存储单元的存储单元区域的半导体衬底和包含用于控制存储单元的外围电路的外围电路区域; 覆盖外围电路区域并且不存在于存储单元区域中的绝缘层; 保护层有效地蚀刻绝缘层并覆盖存储单元区域中的字线导体图案和位线导体图案的顶表面和侧表面; 接触孔，其具有由覆盖所述存储单元区域中的字线导体图案的侧表面的保护层之一限定的圆周，所述接触孔延伸到所述半导体衬底中的扩散区域; 并且电容器元件的存储电极通过接触孔连接到扩散区域。 还公开了制造半导体器件的工艺。

    Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
    15.
    发明授权
    Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
    配有参考电池和负载平衡电路的多值非易失性半导体存储器件

    公开(公告)号：US07307885B2

    公开(公告)日：2007-12-11

    申请号：US11063999

    申请日：2005-02-24

    申请人： Toshimi Ikeda ,  Atsushi Hatakeyama ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    发明人： Toshimi Ikeda ,  Atsushi Hatakeyama ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    IPC分类号： G11C16/28

    CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C2207/002

    摘要： A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.

    摘要翻译： 非易失性半导体存储器件包括保持存储单元信息的多个存储器单元，连接到多个存储器单元的多个位线，多个位线包括与多个存储器单元中选择的一个存储单元相连的第一位线 以及连接到未选择的存储器单元的多个第二位线，分别提供不同参考电流的多个参考单元和读出电路，其中当读取存储单元信息时，读出电路耦合到 所述第一位线连接到所选择的存储器单元，并且通过连接到所述未选择的存储器单元的所述多个第二位线之一耦合到所述多个参考单元中的一个。

    Memory device
    17.
    发明申请
    Memory device 失效
    内存设备

    公开(公告)号：US20050141306A1

    公开(公告)日：2005-06-30

    申请号：US11069940

    申请日：2005-03-03

    申请人： Atsushi Hatakeyama ,  Toshimi Ikeda ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    发明人： Atsushi Hatakeyama ,  Toshimi Ikeda ,  Nobutaka Taniguchi ,  Akira Kikutake ,  Kuninori Kawabata ,  Atsushi Takeuchi

    IPC分类号： G11C5/06 ,  G11C16/06 ,  G11C16/28

    CPC分类号： G11C16/28

    摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

    摘要翻译： 存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103） ）。 预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。 负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。 放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

    Method of manufacturing helical gears by compacting powder materials
    18.
    发明授权
    Method of manufacturing helical gears by compacting powder materials 失效
    通过压实粉末材料制造斜齿轮的方法

    公开(公告)号：US06383447B1

    公开(公告)日：2002-05-07

    申请号：US09610474

    申请日：2000-07-05

    申请人： Toyoshige Nakata ,  Tadaaki Shimada ,  Tatsuhiro Iio ,  Toshimasa Fujita ,  Toshimi Ikeda

    发明人： Toyoshige Nakata ,  Tadaaki Shimada ,  Tatsuhiro Iio ,  Toshimasa Fujita ,  Toshimi Ikeda

    IPC分类号： B22F302

    CPC分类号： B30B11/02 ,  B22F5/08

    摘要： An intermediary die 10 is provided with inner circumferential helical teeth r, a lower punch 7 is provided with outer circumferential helical teeth p, and an upper punch 8 is provided with outer circumferential helical teeth q, respectively. When the intermediary die 10, the lower punch 7 and the upper punch 8 all engage to manufacture helical gears by compacting powdered materials, lateral displacement (phase displacement) of a phase guide 11 which is adapted to engage with the upper outer punch 8a, is forcibly corrected to allow it to return to its original position, from the time when the load of the upper outer punch 8a is reduced to when the intermediary die 10 is released. There is also provided an escape surface on the pressing surface of the upper outer punch 8a. The escape surface is designed to reduce the slide contact force developed on a compacted product Ga when the upper outer punch 8a and the compacted product Ga are respectively displaced in a lateral direction.

    摘要翻译： 中间模具10设置有内周螺旋齿r，下冲头7设置有外周螺旋齿p，上冲头8分别设置有外周螺旋齿q。 当中间模具10，下冲头7和上冲头8都接合以通过压实粉末材料制造斜齿轮时，适于与上外冲头8a接合的相导向件11的横向位移（相位移动）是 从上部外冲头8a的负载减小到中间模具10被释放的时刻被强制地修正为允许其返回到其原始位置。 另外，在上外侧冲头8a的按压面上设置有脱离面。 逃逸面被设计成当上部外冲头8a和压制产品Ga分别沿横向方向移位时，减小在压制产品Ga上产生的滑动接触力。

    Semiconductor device and process of producing same
    20.
    发明授权
    Semiconductor device and process of producing same 失效
    半导体器件及其制造方法

    公开(公告)号：US5550395A

    公开(公告)日：1996-08-27

    申请号：US376082

    申请日：1995-01-20

    申请人： Taiji Ema ,  Toshimi Ikeda

    发明人： Taiji Ema ,  Toshimi Ikeda

    IPC分类号： H01L21/8244 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/105 ,  H01L27/10817 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/86

    摘要： A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covers the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括具有存储单元区域的半导体衬底和围绕存储单元区域的电路区域，其间插入有边界区域。 第一导电层覆盖存储单元区域并延伸到边界区域上。 第一绝缘层覆盖周围电路区域和第一导电层的延伸部分的一部分。 第二绝缘层覆盖第一绝缘层和第一导电层。 通过第一绝缘层和第二绝缘层形成通孔。 第二导电层经由通孔与另一导电层电连接，并从存储单元区域延伸到周围电路区域。 还公开了制造半导体器件的工艺。