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公开(公告)号：US09966986B1
公开(公告)日：2018-05-08
申请号：US15389708
申请日：2016-12-23
Applicant: MEDIATEK INC.
Inventor： Shih-Chi Shen , Shao-Wei Feng , Chun-Ming Kuo , Chi-Hsueh Wang , Ang-Sheng Lin
CPC classification number: H04B1/40 , H03L7/0994 , H03L7/18 , H03L2207/50 , H04W52/02 , H04W52/0216 , H04W52/0235 , H04W52/0274 , H04W52/0287
Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.
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公开(公告)号：US20170090426A1
公开(公告)日：2017-03-30
申请号：US15244132
申请日：2016-08-23
Applicant: MEDIATEK Inc.
Inventor： Yun-Chen Chuang , Ang-Sheng Lin
CPC classification number: G04F10/005 , H03L7/085 , H03L7/16 , H03L2207/50
Abstract: A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.
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公开(公告)号：US20160336914A1
公开(公告)日：2016-11-17
申请号：US15050436
申请日：2016-02-22
Applicant: MEDIATEK INC.
Inventor： Kun-Yin Wang , Wei-Hao Chiu , Ang-Sheng Lin
IPC: H03H7/01
CPC classification number: H03H7/0115 , H01F17/0006 , H01F2017/0073 , H03H5/12
Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.
Abstract translation: 电感电容器（LC）箱包括第一电感器和第一可调电容阵列。 第一电感器具有第一端子和第二端子，并且第一可调谐电容阵列具有第一端子和第二端子。 第一可调电容阵列处于从第一电感器的第一端子和第二端子之间的第一点分支的路径，第一可调谐电容阵列的第一端子耦合到第一点，而第一可调电容阵列的第二端子 可调电容阵列和第一电感器的第二端耦合到参考电压。
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公开(公告)号：US20140070973A1
公开(公告)日：2014-03-13
申请号：US13802948
申请日：2013-03-14
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin
IPC: H03D7/14
CPC classification number: H03D7/1491 , H03D7/1441 , H03D7/1458
Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.
Abstract translation: 信号混合电路，其通过混频器块混合输入信号和振荡信号以提供混合信号。 每个混合器块包括求和节点和电路单元; 求和节点被布置成通过对输入信号和振荡信号求和来提供和信号，并且电路单元被布置成响应于振荡信号的交替而在第一状态和第二状态之间交替; 其中所述电路单元被布置为响应于在所述第一状态期间的所述和信号而提供对所述混合信号的驱动贡献，并且在所述第二状态期间停止提供驱动贡献。 还公开了相关联的转换器，例如数模转换器。
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15.发明公开公开(公告)号：US20240171162A1
公开(公告)日：2024-05-23
申请号：US18234346
申请日：2023-08-15
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Song-Yu Yang , Ang-Sheng Lin
CPC classification number: H03K5/01 , H03L7/08 , H03K2005/00058
Abstract: A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.
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Patent Agency Ranking
公开(公告)号：US11837995B2
公开(公告)日：2023-12-05
申请号：US17730221
申请日：2022-04-27
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Song-Yu Yang , Ang-Sheng Lin , Yi-Chien Tsai
CPC classification number: H03B5/08 , H01F27/2823 , H01F27/40 , H03B5/1265 , H03B5/1268 , H03B2200/009
Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
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公开(公告)号：US20220385233A1
公开(公告)日：2022-12-01
申请号：US17730221
申请日：2022-04-27
Applicant: MEDIATEK INC.
Inventor： Hao-Wei Huang , Song-Yu Yang , Ang-Sheng Lin , Yi-Chien Tsai
Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
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18.发明授权公开(公告)号：US11456750B2
公开(公告)日：2022-09-27
申请号：US17488339
申请日：2021-09-29
Applicant: MEDIATEK INC.
Inventor： Ang-Sheng Lin , Chun-Wei Chang , Tzu-Chan Chueh
Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
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19.发明授权公开(公告)号：US11223362B2
公开(公告)日：2022-01-11
申请号：US17242395
申请日：2021-04-28
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin , Tzu-Chan Chueh
Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.
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公开(公告)号：US09948265B2
公开(公告)日：2018-04-17
申请号：US15050436
申请日：2016-02-22
Applicant: MEDIATEK INC.
Inventor： Kun-Yin Wang , Wei-Hao Chiu , Ang-Sheng Lin
CPC classification number: H03H7/0115 , H01F17/0006 , H01F2017/0073 , H03H5/12
Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.
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