公开(公告)号：US20140253218A1

公开(公告)日：2014-09-11

申请号：US14202634

申请日：2014-03-10

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Joe Depew ,  Terry L. Cleveland

IPC: H01L29/78 ,  H03K17/10 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L24/13 ,  H01L24/16 ,  H01L29/41758 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7817 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2924/13091 ,  H03K17/102 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An improved field effect transistor (FET) is provided by segmenting the gates of a power FET wherein a controller can “decide” how much of the FET to use, thus increasing efficiency.

Abstract translation: 通过分割功率FET的栅极来提供改进的场效应晶体管（FET），其中控制器可以“决定”使用多少FET，从而提高效率。

公开(公告)号：US20130314263A1

公开(公告)日：2013-11-28

申请号：US13897955

申请日：2013-05-20

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix

IPC: H03M1/78

CPC classification number: H03M1/785 ,  H03M1/06 ,  H03M1/682 ,  H03M1/765

Abstract: A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.

Abstract translation: 数模转换器（DAC）具有带有多个串联电阻器的MSB电阻梯，其中MSB电阻器梯形耦合在第一和第二参考电位之间，LSB电阻梯与多个串联连接的电阻， 以及多个开关单元，用于将MSB电阻梯的串联电阻器中的一个连接到LSB电阻梯，其中每个开关单元具有用于将相关联的MSB电阻器的第一端子与LSB的第一端子连接的第一开关 电阻梯和第二开关，用于将相关联的MSB电阻器的第二端子连接到LSB电阻器的第二端子，并且其中每个开关被配置为当开关时LSB电阻器梯形电阻器的电阻值类似的电阻器。

公开(公告)号：US10446497B2

公开(公告)日：2019-10-15

申请号：US15471726

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Dan Grimm ,  Gregory Dix

IPC: H01L29/78 ,  H01L23/535 ,  H01L21/265 ,  H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L25/065 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L23/00 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture. Some embodiments may include: depositing a base within an epitaxial layer; implanting a source implant extending into the base, wherein the epitaxial layer, the base, and the source implant form a continuous plane surface; depositing an insulating layer on the continuous plane surface forming a gate in contact with both the epitaxial layer and the base; opening a contact groove through the insulating layer to expose a central portion of the source implant; depositing a layer of photoresist on top of the insulating layer above exposed portions of the source implant; patterning a set of stripes in the photoresist, each stripe perpendicular to the contact groove; etching the set of stripes with an etch chemistry selective to the insulating layer; and filling the contact groove with a conductive material creating a base-source contact groove reaching through the insulating layer to the surface of the source implant and comprising a plurality of sections spaced apart from each other reaching through the source implant into the base.

公开(公告)号：US20170287834A1

公开(公告)日：2017-10-05

申请号：US15471634

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Dan Grimm ,  Gregory Dix ,  Rodney Schroeder

IPC: H01L23/535 ,  H01L29/06 ,  H01L23/00 ,  H01L27/088 ,  H01L25/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L25/065

CPC classification number: H01L23/535 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/4824 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/78 ,  H01L2224/48137 ,  H01L2225/06506 ,  H01L2225/06582 ,  H01L2924/13091

Abstract: The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET). Some embodiments may include a power MOSFET with transistor cells, each cell comprising a source and a drain region; a first dielectric layer disposed atop the transistor cells; a silicon rich oxide layer on the first dielectric layer; grooves through the multi-layered dielectric, each groove above a respective source or drain region and filled with a conductive material; a second dielectric layer atop the multi-layered dielectric; openings in the second dielectric layer, each opening exposing a contact area of one of the plurality of grooves; and a metal layer disposed atop the second dielectric layer and filling the openings. The metal layer may form at least one drain metal wire and at least one source metal wire. The at least one drain metal wire may connect two drain regions through respective grooves. The at least one source metal wire may connect two source regions through respective grooves. Each groove has a length extending from the at least one drain metal wire to the at least one source metal wire in an adjacent pair.

公开(公告)号：US09337253B2

公开(公告)日：2016-05-10

申请号：US14199522

申请日：2014-03-06

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Randy Yach

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/64 ,  H01G4/40 ,  H01G4/06 ,  H03K17/689 ,  H01L23/00 ,  H04L25/02

CPC classification number: H01L28/40 ,  H01G4/06 ,  H01G4/40 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/3011 ,  H03K17/689 ,  H04L25/0266 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Abstract translation: 在初级集成电路管芯的表面上形成至少一个高压额定绝缘电容器。 隔离电容器AC将第一电压域中的初级集成电路耦合到第二电压域中的第二集成电路。 隔离电容器DC将初级集成电路与第二集成电路管芯隔离。

公开(公告)号：US08937351B2

公开(公告)日：2015-01-20

申请号：US13784723

申请日：2013-03-04

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Harold Kline ,  Dan Grimm ,  Roger Melcher ,  Jacob L. Williams

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract translation: 功率金属氧化物半导体（MOS）场效应晶体管（FET）具有多个晶体管单元，每个单元具有通过硅晶片管芯的表面接触的源区和漏区，第一介电层为 设置在硅晶片模具的表面上，并且在源极区域和漏极区域上方的第一电介质层中分别形成有多个沟槽，并且填充有导电材料。第二电介质层设置在第一电介质的表面上 并且具有用于将接触区域暴露于凹槽的开口。 金属层设置在第二电介质层的表面上并填充开口，其中对金属层进行图案化和蚀刻，以形成分别连接多个晶体管单元的漏极区域和每个源极区域的金属线路，该金属线路通过沟槽 。

公开(公告)号：US20140252551A1

公开(公告)日：2014-09-11

申请号：US14199522

申请日：2014-03-06

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Randy Yach

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01G4/06 ,  H01G4/40 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/3011 ,  H03K17/689 ,  H04L25/0266 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Abstract translation: 在初级集成电路管芯的表面上形成至少一个高压额定绝缘电容器。 隔离电容器AC将第一电压域中的初级集成电路耦合到第二电压域中的第二集成电路。 隔离电容器DC将初级集成电路与第二集成电路管芯隔离。