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    Capacitor Structure With An Extended Dielectric Layer And Method Of Forming A Capacitor Structure
    2.
    发明申请
    Capacitor Structure With An Extended Dielectric Layer And Method Of Forming A Capacitor Structure 有权

    公开(公告)号：US20180226469A1

    公开(公告)日：2018-08-09

    申请号：US15885948

    申请日：2018-02-01

    Applicant: Microchip Technology Incorporated

    Inventor： Randy Yach ,  Rohan Braithwaite

    IPC: H01L49/02 ,  H01L29/94

    CPC classification number: H01L28/60 ,  H01G4/10 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L29/94

    Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.

    Method and apparatus for monitoring semiconductor fabrication
    3.
    发明授权
    Method and apparatus for monitoring semiconductor fabrication 有权
    用于监控半导体制造的方法和装置

    公开(公告)号：US08878183B2

    公开(公告)日：2014-11-04

    申请号：US13831101

    申请日：2013-03-14

    Applicant: Microchip Technology Incorporated

    Inventor： Randy Yach

    IPC: H01L23/58 ,  H01L21/66

    CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.

    Abstract translation: 一种用于半导体制造的过程监控的半导体芯片，具有多个具有多个二极管的阵列，每个二极管形成在芯片中，每个二极管与具有至少一个水平互连的堆叠相关联，堆叠和二极管连接在 串联以形成二极管堆叠组合，其中水平互连具有包含互补掺杂多晶硅部分的水化多晶硅互连以形成反向偏置二极管。

    METHOD AND APPARATUS FOR MONITORING SEMICONDUCTOR FABRICATION
    4.
    发明申请
    METHOD AND APPARATUS FOR MONITORING SEMICONDUCTOR FABRICATION 有权
    用于监测半导体制造的方法和装置

    公开(公告)号：US20140264333A1

    公开(公告)日：2014-09-18

    申请号：US13831101

    申请日：2013-03-14

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Randy Yach

    IPC: H01L21/66

    CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.

    Abstract translation: 一种用于半导体制造的过程监控的半导体芯片，具有多个具有多个二极管的阵列，每个二极管形成在芯片中，每个二极管与具有至少一个水平互连的堆叠相关联，堆叠和二极管连接在 串联以形成二极管堆叠组合，其中水平互连具有包含互补掺杂多晶硅部分的水化多晶硅互连以形成反向偏置二极管。

    Capacitor structure with an extended dielectric layer and method of forming a capacitor structure
    7.
    发明授权
    Capacitor structure with an extended dielectric layer and method of forming a capacitor structure 有权

    公开(公告)号：US10418438B2

    公开(公告)日：2019-09-17

    申请号：US15885948

    申请日：2018-02-01

    Applicant: Microchip Technology Incorporated

    Inventor： Randy Yach ,  Rohan Braithwaite

    IPC: H01L29/94 ,  H01L49/02 ,  H01G4/33 ,  H01G4/10 ,  H01G4/12

    Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.

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