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    Memory Circuitry And Method Used In Forming Memory Circuitry
    12.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240047346A1

    公开(公告)日：2024-02-08

    申请号：US17880444

    申请日：2022-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Rutuparna Narulkar ,  Chandra Tiwari ,  Dmitry Mikulik ,  Erica A. Ellingson ,  Yucheng Wang ,  Mathew Thomas

    IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/5228 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. A lining has a specific resistance of at least 1×104 ohm·m at 20° C. atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. The lining comprises at least one of (a), (b), (c), and (d), where: (a): M1xM2yOz having a specific resistance of at least 1×104 ohm·m at 20° C. and where M1 and M2 are each a different one of Hf, Zr, Al, Ta, Sc, and Y; “z” is greater than zero; and at least one of “x” and “y” is greater than zero; (b) BtCwOv having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “t” and “v” is greater than zero (c): BrCs having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “r” and “s” is greater than zero; and (d): BkChNp having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “k” and “p” is greater than zero. Insulative material in the cavity is directly above the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Conductive vias extend through the insulative material and the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Methods are disclosed.

    Memory arrays and methods of forming memory arrays
    15.
    发明授权
    Memory arrays and methods of forming memory arrays 有权

    公开(公告)号：US11444093B2

    公开(公告)日：2022-09-13

    申请号：US16739581

    申请日：2020-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Tiwari

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. A horizontal pattern of operative memory-cell pillars extends through the insulative tiers and the conductive tiers in individual of the memory blocks. The operative memory-cell pillars have intrinsic compressive mechanical stress. At least one dummy structure in the individual memory blocks extends through at least upper of the insulative tiers and the conductive tiers. The at least one dummy structure is at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern. The at least one dummy structure has intrinsic tensile mechanical stress. Other embodiments, including methods, are disclosed.

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