公开(公告)号：US20190198520A1

公开(公告)日：2019-06-27

申请号：US15948639

申请日：2018-04-09

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02636 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/4991 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US11302708B2

公开(公告)日：2022-04-12

申请号：US16674823

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11529 ,  H01L27/1157

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US20210118892A1

公开(公告)日：2021-04-22

申请号：US17113934

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/1157 ,  H01L29/792 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/51 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11578 ,  H01L27/11524

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

公开(公告)号：US20200185413A1

公开(公告)日：2020-06-11

申请号：US16793560

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200135745A1

公开(公告)日：2020-04-30

申请号：US16177220

申请日：2018-10-31

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Gianpietro Carnevale

IPC: H01L27/1157 ,  G11C16/08 ,  G11C8/14 ,  G06F3/06 ,  H01L27/11573 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11950422B2

公开(公告)日：2024-04-02

申请号：US17973435

申请日：2022-10-25

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H10B43/35 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27

CPC classification number: H10B43/35 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

公开(公告)号：US11515321B2

公开(公告)日：2022-11-29

申请号：US17113934

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11524 ,  H01L29/792 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

公开(公告)号：US10770472B2

公开(公告)日：2020-09-08

申请号：US16177220

申请日：2018-10-31

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Gianpietro Carnevale

IPC: H01L27/1157 ,  G11C16/08 ,  H01L27/11582 ,  G06F3/06 ,  H01L27/11573 ,  G11C8/14

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10665603B2

公开(公告)日：2020-05-26

申请号：US16521441

申请日：2019-07-24

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/11 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/51 ,  H01L21/764

Abstract: Some embodiments include an assembly having a channel to conduct current. The channel includes a first channel portion and a second channel portion. A first memory cell structure is between a first gate and the first channel portion. The first memory cell structure includes a first charge-storage region and a first charge-blocking region. A second memory cell structure is between a second gate and the second channel portion. The second memory cell structure includes a second charge-storage region and a second charge-blocking region. The first and second charge-blocking regions include silicon oxynitride. A void is located between the first and second gates, and between the first and second memory cell structures. Some embodiments include memory arrays (e.g., NAND memory arrays), and some embodiments include methods of forming memory arrays.

公开(公告)号：US10593695B1

公开(公告)日：2020-03-17

申请号：US16162672

申请日：2018-10-17

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.