公开(公告)号：US20210193675A1

公开(公告)日：2021-06-24

申请号：US16723136

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US20200343262A1

公开(公告)日：2020-10-29

申请号：US16927084

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

公开(公告)号：US20190221580A1

公开(公告)日：2019-07-18

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/4975

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20250113487A1

公开(公告)日：2025-04-03

申请号：US18978230

申请日：2024-12-12

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  M. Jared Barclay ,  Bhavesh Bhartia ,  Chet E. Carter ,  John D. Hopkins ,  Andrew Li ,  Haoyu Li ,  Alyssa N. Scarbrough ,  Grady S. Waldo

IPC: H10B43/27 ,  H10B41/27

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

公开(公告)号：US20240162325A1

公开(公告)日：2024-05-16

申请号：US18421820

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Michael A. Lindemann ,  Collin Howder ,  Yoshiaki Fukuzumi ,  Richard J. Hill

IPC: H01L29/45 ,  H01L21/28 ,  H01L29/417 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/458 ,  H01L29/40117 ,  H01L29/41725 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

公开(公告)号：US11948992B2

公开(公告)日：2024-04-02

申请号：US17158918

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Michael A. Lindemann ,  Collin Howder ,  Yoshiaki Fukuzumi ,  Richard J. Hill

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/792 ,  H01L21/28 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/458 ,  H01L29/40117 ,  H01L29/41725 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

公开(公告)号：US20230389318A1

公开(公告)日：2023-11-30

申请号：US18359792

申请日：2023-07-26

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

IPC: H10B43/27 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/50

Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

公开(公告)号：US20230389312A1

公开(公告)日：2023-11-30

申请号：US17751978

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Taehyun Kim

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230337429A1

公开(公告)日：2023-10-19

申请号：US18212899

申请日：2023-06-22

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H10B43/27 ,  H01L21/822 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/8221 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230005956A1

公开(公告)日：2023-01-05

申请号：US17941900

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Justin D. Shepherdson ,  Collin Howder ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/285 ,  H01L27/11519 ,  H01L29/66 ,  H01L21/28

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.